Data transfer control method, and peripheral circuit, data processor and data processing system for the method
AssigneeHitachi, Ltd.
InventorHiroshi Takeda
Life of this patent
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Abstract
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
Claims6
A method of controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the method comprising the steps of:
- sending an access request from the data processor to the memory, the access request including address signals;
- performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals;
- sending the second clock signals from the memory to the data processor;
- transferring data from the memory to the data processor in synchronism with the second clock signals;
- writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals;
- and,
- outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
An apparatus for controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the apparatus further comprising:
- means for sending an access request from the data processor to the memory, the access request including address signals;
- means for performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals;
- means for sending the second clock signals from the memory to the data processor;
- means for transferring data from the memory to the data processor in synchronism with the second clock signals;
- means for writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals;
- and,
- means for outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
Dependencies are inferred from the claim text.