US 5,673,396 AGranted

Adjustable depth/width FIFO buffer for variable width data transfers

AssigneeMotorola, Inc.

InventorsLeonid Smolansky, Shai Kowal, Avner Goren, David Galanti

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Abstract

An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

Claims10

Dependent claims

A data processing system having a first-in, first-out buffer, the

first-in, first-out buffer comprising:
a plurality of storage elements, the plurality of storage elements organized as a first section and a second section, each storage element of the plurality of storage elements having a plurality of input terminals coupled to a first bus, and a plurality of output terminals coupled to a second bus;
and
a control logic circuit, coupled to the plurality of storage elements, for controlling access to the first section and to the second section;
wherein the plurality of storage elements have a first width and a first depth in response to the control logic circuit independently accessing the first and second sections, and the plurality of storage elements have a second width and a second depth in response to the control logic circuit accessing the first and second sections together, and wherein one of either the first depth and the second depth is provided depending which of the first width or second width is used.

2 more elements

A data processing system having an adjustable depth/width first-in, first-out buffer, the adjustable depth/width first-in, first-out buffer comprising:

a first section of storage elements, each storage element of the first section of storage elements for storing a first predetermined number of data bits, the first section of storage elements coupled to a bus;
a second section of storage elements each storage element of the second section of storage elements for storing a second predetermined number of data bits, the second section of storage elements coupled to the bus;
and
a control logic circuit, coupled to the first and second sections of storage elements, the control logic circuit accessing one storage element of the first section of storage elements in response to sampling a first data word from the bus having the first predetermined number of data bits, and the control logic circuit accessing one storage element of both the first and second sections of storage elements together in parallel for storing a second data word from the bus having a third predetermined number of data bits, wherein the third predetermined number of data bits is equal to the first predetermined number plus the second predetermined number, the control logic circuit accessing the first and second sections of storage elements to provide a first depth when sampling the first data word from the bus having the first predetermined number of data bits and the control logic circuit accessing the first and second sections of storage elements to provide a second depth when sampling the second data word from the bus having the third predetermined number of data bits, wherein the first depth is substantially twice the second depth.

1 more element

Dependencies are inferred from the claim text.