Methods and apparatus for resetting a monitored system using a gray code with alternating check bits

A method for resetting a monitored system comprising the steps of:

• operating said monitored system to generate at least two check bits which progress through a defined series of states with each state differing from adjacent states by only one bit position;
• operating a counter to count pulses from a source of periodic pulses;
• periodically sampling said at least two check bits generated by operation of said monitored system;
• generating a pass signal for each sample of said at least two check bits wherein only one of said at least two check bits changes state;
• clearing said counter in response to each pass signal;
• generating an error signal on a second output connected to said output logic for each sample of said at least two check bits wherein more than one of said at least two check bits has changed state;
• and
• generating a reset signal for said monitored system in response to an overflow of said counter or said error signal from said monitored system error detector.

A circuit for resetting a monitored system comprising:

• an output logic circuit for generating a reset signal for said monitored system;
• a clock circuit for generating a series of periodic pulses;
• a clock rate counter circuit for counting periodic pulses from said clock circuit to generate clock pulses;
• a counter circuit for counting said clock pulses, said counter circuit having a clear input and an overflow output connected to said output logic circuit;
• and
• a monitored system error detector circuit responsive to said clock pulses for sampling at least two check bits from said monitored system which normally operates to generate said at least two check bits in a series of states with successive states differing from one another by only one bit, said error detector circuit generating a pass signal on a first output coupled to said clear input of said counter circuit for each sample of said at least two check bits wherein only one of said at least two check bits changes state from the succeeding sample and generating an error signal on a second output connected to said output logic for each sample of said at least two check bits wherein more than one of said at least two check bits has changed state from the succeeding sample, said output logic generating a reset signal for said monitored system in response to an overflow of said counter or said error signal from said monitored system error detector.