Memory testing in a multiple processor computer system
AssigneeIntel Corporation
InventorsRaghu Murthi, Scott Tetrick
Life of this patent
Estimating the term…
Abstract
Testing of shared memory (RAM) in a multiple processor computer system is achieved by partitioning the memory and allocating the memory portions to respective processors in the system. Each processor performs testing of its allocated memory portion simultaneously with the other processors in order to reduce the time required to complete the memory test.
Claims18
In a multiple processor computer system, an initialization method comprising the steps of:
- allocating respective portions of shared memory to each of a plurality of processors;
- and
- testing said respective portions of shared memory in each of said plurality of processors by time division multiplexed access to said shared memory.
A computer system comprising:
- a plurality of processors coupled to a bus;
- a first memory coupled to said bus;
- a second memory coupled to said bus;
- and
- program instructions stored in said second memory, said program instructions executed by each of said plurality of processors to test respective portions of said first memory by time division multiplexed access to said first memory.
A computer system comprising:
- a plurality of processors coupled to a bus;
- a first memory coupled to said bus;
- a memory controller coupled between said first memory and said bus, said memory controller writing to and reading from said first memory in response to time division multiplexed signals received from said plurality of processors;
- and
- a second memory coupled to said bus containing initialization instructions, said instructions executed by said plurality of processors such that each of said plurality of processors communicates with said memory controller means to test respective portions of said first memory over substantially the same time interval.
A method for testing memory in a multiple processor computer system having shared memory accessible on a common bus, comprising the steps of:
- assigning to each of a plurality of processors a respective separate portion of said shared memory;
- each of said plurality of processors writing data to and subsequently reading data from substantially every memory location of said respective separate portion of memory, the writing and reading of said data being time division multiplexed as between said plurality of processors;
- and comparing in each of said plurality of processors said data written and said data read from said respective separate portion of said shared memory .
Dependencies are inferred from the claim text.