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US 5,673,321 AGranted
Efficient selection and mixing of multiple sub-word items packed into two or more computer words
AssigneeHewlett-Packard Company
InventorRuby Bei-Loh Lee
Life of this patent
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Abstract
A computer system facilitates efficient mixing of multiple sub-word items. Mixing circuitry is connected to a plurality of registers and a result register. The mixing circuitry mixes multiple sub-word items packed into the plurality of registers. The multiple sub-word items, when mixed, are placed in the result register. In the preferred embodiment, the mixing circuitry is implemented using a plurality of multiplexors. Control circuitry, connected to the control inputs of the multiplexors, generates control signals which control the mixing of multiple sub-word items by the multiplexors.
Claims17
A computer implemented comprising the steps of:
- (a) in response to a mix half-word left instruction, concatenating a first half-word of a first double-word, a first half-word of a second double-word, a third half-word of the first double-word and a third half-word of the second double-word and placing the result in a third double-word;
- and,
- (b) in response to a mix half-word right instruction, concatenating a second half-word of the first double-word, of second half-word of the second double-word, a fourth half-word of the first double-word and a fourth half-word of the second double-word and placing the result in the third double-word.
A computing system comprising:
- a first doubleword register;
- a second doubleword register;
- a third doubleword register;
- mix circuitry, coupled to the first doubleword register, the second doubleword register and the third doubleword register, for, in response to a mix half-word left instruction, concatenating a first half-word of the first doubleword register, a first half-word of the second doubleword register, a third half-word of the first doubleword register and a third half-word of the second doubleword register and placing a result in the third doubleword register.
1 more element
A computing system comprising:
- a first doubleword register;
- a second doubleword register;
- a third doubleword register;
- mix circuitry, coupled to the first doubleword register, the second doubleword register and the third doubleword register, for, in response to a mix byte left instruction, concatenating a first byte of the first doubleword register, a first byte of the second doubleword register, a third byte of the first doubleword register, a third byte of the second doubleword register, a fifth byte of the first doubleword register, a fifth byte of the second doubleword register, a seventh byte of the first doubleword register and a seventh byte of the second doubleword register and placing a result in the third doubleword register.
1 more element
A computing system comprising:
- a first doubleword register;
- a second doubleword register;
- a third doubleword register;
- mix circuitry, coupled to the first doubleword register, the second doubleword register and the third doubleword register, for, in response to a mix half-word right instruction, concatenating a second half-word of the first doubleword, register, a second half-word of the second doubleword register, a fourth half-word of the first doubleword register and a fourth half-word of the second doubleword register and placing a result in the third doubleword register.
1 more element
A computing system comprising:
- a first doubleword register;
- a second doubleword register;
- a third doubleword register;
- mix circuitry, coupled to the first doubleword register, the second doubleword register and the third doubleword register, for, in response to a mix byte right instruction, concatenates a second byte of the first doubleword register, a second byte of the second doubleword register, a fourth byte of the first doubleword register, a fourth byte of the second doubleword register, a sixth byte of the first doubleword register, a sixth byte of the second doubleword register, an eighth byte of the first doubleword register and an eighth byte of the second doubleword register and places a result in the third doubleword register.
1 more element
A computer implemented method comprising the steps of:
- (a) in response to a mix byte left instruction, concatenating a first byte of a first doubleword, a first byte of a second doubleword, a third byte of the first doubleword, a third byte of the second doubleword, a fifth byte of the first doubleword, a fifth byte of the second doubleword, a seventh byte of the first doubleword and a seventh byte of the second doubleword and placing the result in a third doubleword;
- and,
- (b) in response to a mix byte right instruction, concatenating a second byte of the first doubleword, a second byte of the second doubleword, a fourth byte of the first doubleword, a fourth byte of the second doubleword, a sixth byte of the first doubleword, a sixth byte of the second doubleword, an eighth byte of the first doubleword and an eighth byte of the second doubleword and placing the result in the third doubleword.
A computing system comprising:
- a first register;
- a second register;
- a third register
- mix circuitry, coupled to the first register, the second register and the third register, for mixing multiple sub-word items packed into the first register and the second register, the multiple sub-word items when mixed being placed in the third register, the mixing circuitry comprising:
- a plurality of multiplexors arranged in rows, wherein
- a first portion of the plurality of multiplexors being arranged in a first row of the multiplexors, each multiplexor in the first portion receiving a multiple sub-word item from each of the first register and the second register, and,
- a second portion of the plurality of multiplexors being arranged in a last row of the multiplexors, each multiplexor in the last portion placing a sub-word item within the third register.
4 more elements
A computing system comprising:
- a first register;
- a second register;
- a third register
- mix circuitry, coupled to the first register, the second register and the third register, for mixing multiple sub-word items packed into the first register and the second register, the multiple sub-word items when mixed being placed in the third register, the mixing circuitry comprising:
- a selecting means for making a selection of which sub-word items to be placed in the third register, wherein the selection varies depending upon a control value placed on control inputs to the selecting means, and
- control circuitry, coupled to the control inputs to the selecting means, for placing the control value on the control inputs.
3 more elements
Dependencies are inferred from the claim text.