Frame synchronization circuit for digital communication system

A frame synchronization circuit for use in an ISDN (Integrated Services Digital Network) primary rate interface, for detecting frame synchronization bits allotted in particular positions within a receiving data string, said frame synchronization circuit comprising:

• a shift register which receives and stores said receiving data string, and then outputs a parallel data string of 6 bits disposed in a 772 bit cycle within the receiving data string;
• and
• a synchronization pattern detection circuit which receives said parallel data string output from said shift register in synchronization with a clock signal and makes decisions simultaneously or at one time on matching/non-matching between said parallel data string of 6 bits and any one of 6 kinds of predetermined synchronization patterns of 6 bits, said 6 kinds of predetermined synchronization patterns having been established in advance in said synchronization pattern detection circuit;
• said synchronization pattern detection circuit comprising:
• a plurality inverters, each of which is coupled to receive one bit of said parallel data string of 6 bits;
• a plurality of NAND gates, each of which having a plurality of inputs, one of said inputs being coupled to an output of one of said inverters or to receive one bit of said parallel data string of 6 bits, and another of said inputs being coupled to an output of one of the inverters or to receive one bit of said parallel data string of 6 bits;
• a plurality of Exclusive NOR gates, each having two inputs, each of said inputs being coupled to receive one bit of said parallel data string of 6 bits;
• a plurality of NOR gates, each of which having a plurality of inputs, each of said inputs receiving an output of one of said NAND gates or an output of one of said Exclusive NOR gates;
• and
• an OR gate having a plurality of inputs, each for receiving an output of said NOR gates, and having an output for outputting an output indicating matching or non-matching between said parallel data string of 6 bits and said any one of six kinds of predetermined synchronization patterns of 6 bits.