US 5,673,295 A · Method and apparatus for generating and synchronizing a plurality of digital signals

Abstract

A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay. Each data channel also has an input for receiving a data bit, a controller for receiving the timing information which allows selection of the one internal clock signal which most closely matches the timing information, and an output port coupled to the HME. The timing multiplexer also has a dummy channel from which the sensed delay is determined. The sensed delay approximates the throughput delay. The dummy channel receives the first one of the internal clock signals and provides the feedback control signal. Finally, the hardware interface apparatus includes a timing adjustment control circuit for selectively delaying the output signal in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

Claims6

Dependent claims

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising:

a. a clock generating circuit comprising:
(1) an input for receiving a master clock signal having a predetermined range of frequencies;
(2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals;
and
(3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay;
and
b. a timing multiplexer, coupled to receive the internal clock signals from the clock generating circuit, the timing multiplexer comprising:
(1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising:
(a) a data channel input for receiving a predetermined one of the data bits;
(b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information;
and
(c) an output port for coupling an output signal representative of the predetermined one of the data bit to the HME at the predetermined time;
and
(2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal.

11 more elements

a. at least two clock generating circuits, each clock generating circuit comprising:
(1) an input for receiving a master clock signal having a predetermined first period;
(2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals;
and
(3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay;
and
b. at least two timing multiplexers, coupled to receive the internal clock signals from one of the clock generating circuits, each timing multiplexer comprising:
(1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising:
(a) a data channel input for receiving a predetermined one of the data bits;
(b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information;
and
(c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time;
and
(2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal,
wherein the throughput delays for each of the timing multiplexers need not be identical.

12 more elements

a. at least two clock generating circuits, each clock generating circuit comprising:
(1) an input for receiving a master clock signal having a predetermined first period;
(2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals;
and
(3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay;
b. at least two timing multiplexers, each coupled to receive the internal clock signals from a respective one of the clock generating circuits, each timing multiplexer comprising:
(1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising:
(a) a data channel input for receiving a predetermined one of the data bits;
(b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information;
and
(c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time;
(2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal,
wherein the throughput delays for each of the timing multiplexers need not be identical;
and
c. a timing adjustment control circuit coupled to each of the timing multiplexers for selectively delaying the data bits as input signals in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

12 more elements

Dependencies are inferred from the claim text.

Method and apparatus for generating and synchronizing a plurality of digital signals

Life of this patent

Method and apparatus for generating and synchronizing a plurality of digital signals

Life of this patent

Abstract

Claims6