Boundary-scan-compliant multi-chip module
AssigneeLucent Technologies Inc.
InventorsNajmi Taher Jarwala, Chi Wang Yau
Life of this patent
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Abstract
A multi-chip module (10), having n semiconductor chips 14.sub.1 -14.sub.n, each chip having a Boundary-Scan architecture, is rendered Boundary-Scan-compliant both as a circuit board and as a macro-device by the addition of a bypass circuit (36, 36' and 36"). During selected intervals when the module (10) is to be Boundary-Scan-compliant as a macro-device, the bypass circuit operates to bypass the Test Data Input (18) to the Test Data Output (34) of each of n-1 chips. During other than the selected intervals, the bypass circuit allows test information applied to the Test Data Input of each of the chips to be shifted through the chip and to appear at its Test Data Output to facilitate Boundary-Scan compliance of the module as a circuit board.
Claims5
A multi-chip module having external inputs/outputs and being Boundary-Scan compliant both as a circuit board and as a macro device, comprising:
- n semiconductor chips (where n is an integer), each of said chips having inputs/outputs, some of which form said external inputs/outputs of said module, said chips each having a Boundary-Scan architecture and coupled in a Boundary-Scan chain, each of said chips including a Test Data Input (TDI) and a Test Data Output (TDO), a first one of said chips in the chain receiving a stream of test information bits at its TDI via a TDI associated with the module for shifting through the chain, a last one of said chips in the chain shifting out slid stream of test information bits from its TDO to a TDO associated with the module, and each of said chips in the chain other than said first and said last chips having its TDO coupled to the TDI of a downstream chip;
- a bypass circuit associated with at least n-1 of said chips for causing the stream of test information bits to be bypassed directly from the TDI to the TDO of each of n-1 of said chips during selected intervals so that said chips collectively appear as a single Boundary-Scan-compliant macro device during said selected intervals, including:
- a Test Data Input (TDI) forming the TDI associated with the module for receiving said stream of test information bits for selected transmission to the chain of said chips;
- an instruction register for storing an instruction contained within the stream of test information bits applied to the TDI of the bypass circuit (which also forms the TDI associated with the module);
- a bypass register for storing a bit of information contained in said stream of test information bits;
- a Test Data Output (TDO) at which information contained in one of said instruction and bypass registers is selectively supplied to the TDI of a first one of said chips in the chain;
- a multiplexer having a first input coupled to the TDO of the bypass circuit and a second input coupled to the TDO of a last one of said chips in the chain, the multiplexer passing a signal at a separate one of its inputs to its output (which serves as a Test Data Output (TDO) for the module) in response to a control signal applied to the multiplexer;
- and
- a decoder for generating the control signal for the multiplexer in accordance with the instruction contained in the instruction register circuit and in accordance with the state of a Boundary-Scan compliance enable signal supplied to the decoder to establish whether the module is to be Boundary-Scan-compliant as a macro-device or a circuit board and;
- a module-level Boundary-Scan register having a first plurality of register elements each associated with one of said external inputs/outputs of the module and a second plurality of register elements each associated with one of said inputs/outputs that does not form an external input/output of said module, each of said second register elements being controllable for setting to a safe value during testing.
Dependencies are inferred from the claim text.