Test method for semiconductor device

A semiconductor device with a test circuit comprising:

• a processor providing a control function for the testing of the semiconductor device;
• a test data storage area, connected to said processor, said test data storage area storing input test data and test result data;
• a plurality of functional blocks, each of said functional blocks including,
• a logical circuit to be tested,
• a first storage area on an input side of said logical circuit, said first storage area storing said input test data,
• a second storage area on an output side of said logical circuit, said second storage area storing said test result data;
• a selector connected between said test data storage area and said functional blocks and receiving multiple inputs from said test data storage area;
• a shift counter containing the number of scan clock signals to be generated, connected to said plurality of functional blocks, said test data storage area and said processor;
• a transfer register connected to said selector, said functional blocks and said processor, said transfer register storing data indicating transfer direction of test data into or out of said functional blocks;
• a mode register connected to said functional blocks and said processor, said mode register storing data indicating a scan operation mode or a normal operation mode, said mode register being loaded by said processor;
• and
• a select register connected to said selector, said test data storage area and said processor, said select register storing data selecting test data from said test data storage area to be provided through said selector to said functional blocks,
• and wherein said test data storage area, said shift counter, said transfer register and said select register are accessed by instructions programmed by using instructions of an instruction set of said processor to control testing.

A method of testing a semiconductor device with a test circuit, with a processor providing test control, the method comprising the steps of:

• loading input test data into a test data storage area from said processor based on instructions programmed by using instructions of an instruction set of the processor;
• loading a transfer register from said processor with data indicating that a transfer direction of test data is into a functional block to be tested based on instructions programmed by using instructions of the instruction set of the processor;
• loading a mode register from said processor with data indicating a scan operation mode based on instructions programmed by using instructions of the instruction set of the processor;
• loading a select register from said processor, with data indicating which data from said test data storage area is to be provided through said selector to said functional block based on instructions programmed by using instructions of the instruction set of the processor;
• loading a shift counter from said processor with data indicating the number of scan clock signals to be generated based on instructions programmed by using instructions of the instruction set of the processor;
• scanning input test data, selected according to said select register, from said test data storage area into a first storage area on an input side of a logical circuit to be tested in said functional block based on instructions programmed by using instructions of the instruction set of the processor;
• loading said mode register, from said processor, with data indicating a normal operation mode based on instructions programmed by using instructions of the instruction set of the processor;
• generating one scan clock signal in normal operation mode based on instructions programmed by using instructions of the instruction set of the processor;
• reloading said transfer register from said processor with data indicating that the transfer direction of test data is out of said functional block based on instructions programmed by using instructions of the instruction set of the processor;
• reloading said mode register, from said processor, with data indicating a scan operation mode based on instructions programmed by using instructions of the instruction set of the processor;
• scanning test result data, from a second storage area on an output side of said logical circuit, into said test data storage area based on instructions programmed by using instructions of the instruction set of the processor;
• and
• analyzing said test result data in said test data storage area by said processor based on instructions programmed by using instructions of the instruction set of the processor.