Clock controller for embedded test

Abstract

An embedded electronic system includes a clock controller embedded in the same matrix material as a subsystem under test and the measurement devices needed to test it. This embedded clock controller controls the distribution and gating of a system clock that runs continuously, but is only supplied to the subsystem under test during normal operation or during pre-programmed intervals of testing operations. A test data bus supplies test data and a path for the return of test results. The test data supplied to the clock controller includes information to control time relationships between its trigger and gated clock outputs. Different versions of the clock controller are described, one for use with a serial test data bus and another for use with a parallel test data bus. The clock controller can also be configured to produce trigger signals with timing appropriate to operating either edge-sensitive or level-sensitive measurement devices. Also, new test commands can be loaded while a previous test is running, or tests can be repeated without changing the test data supplied. Multiple clock controllers can be configured to control the operation of multiple measurement devices in various timing relationships.

Dependencies are inferred from the claim text.