High speed pattern generator

A high speed pattern generator for generating a test pattern and an expected data pattern wherein the test pattern is applied to an electronic device to be tested and the resulted output of the electronics device is compared with the expected data pattern by a comparator, said pattern generator comprising:

• an address generator (13) for generating address data of said test pattern, said address generator including a pipeline having a plurality of sequential stages wherein a plurality of instructions are executed in said sequential stages at the same time;
• an operation control memory (12) that stores a part of said instructions to be processed in said address generator (13);
• a save register (300) that stores branch destination data in a sequence control section (11) in response to a match signal from the comparator (4), said sequence control section accesses said operation control memory to read said instructions;
• and
• an inhibit gate (500) that prevents an initial clock generator (161) from generating an initial clock for driving said pipeline in said address generator to fill in commands in said plurality of sequential stages in response to the match signal.