US 5,673,270 AGranted

Semiconductor memory device having register for holding test resultant signal

AssigneeNEC Corporation

InventorAkira Tsujimoto

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Abstract

Disclosed herein is a semiconductor memory device having a memory cell array, a write/read circuit which writes during a test mode a plurality of identical data to the memory cell array in response to input addresses and reads the plurality of data from the memory cell array in response to the same addresses, a comparison data register which stores data identical to the plurality of data written to the memory cell array during the test mode, a decision circuit which compares the plurality of data read from memory cell array and the data stored in the comparison data register to decide whether the data compared coincide, and outputs a decision signal, and a decision result register which is reset immediately after the start of the test mode and is set to a set level in response to a decision signal of noncoincidence level and remains set state until it is reset again.

Claims7

Dependent claims

A semiconductor memory device, having a normal operation mode and a test mode, comprising:

a plurality of memory cells,
means for detecting initiation of said test mode and for producing a test mode signal having a first level and a second level, wherein a test operation is repeated a plurality of times according to a predetermined test pattern, said test operation including a data write operation and a data read operation,
write/read means for writing one bit data into at least one of said memory cells and for reading out one bit data from said at least one of said memory cells in response to said test mode signal having said first level, and for writing test data into a plurality of said memory cells and for simultaneously reading out data from said plurality of said memory cells in response to said test mode signal having said second level,
a comparison data register for receiving and temporarily storing said test data,
a decision circuit, operating each time said data is read from said plurality of said memory cells, which compares said data read out from said plurality of said memory cells with said test data stored in said comparison data register and which outputs a decision signal having a first level when said data and said test data are coincident with one another and having a second level when said data and said test data supplied to said decision circuit are not coincident with one another,
a decision result register, coupled to said decision circuit, which is reset when said test mode signal is at second level, and which is set to hold said decision signal when said decision signal of said second level is received,
control means for outputting a control signal when said test mode is completed, and
an output circuit, responsive to said control signal, to produce an output signal, supplied to an input/output terminal, indicative of a state of said decision result register.

5 more elements

A semiconductor memory device comprising:

a memory cell array which writes in bit parallel fashion and stores a supplied unit data of a predetermined set of plural bits to predetermined addresses, and reads said unit data stored in said predetermined addresses in bit parallel fashion;
data input control means for supplying to said memory cell array said unit data of identical level for all bits supplied externally during a test mode;
a data register which fetches and outputs comparison data, externally supplied during said test mode, at predetermined timings;
a decision circuit which compares said comparison data from said data register with said unit data read from said memory cell array a plurality of times according to a predetermined test pattern, and which outputs a decision signal having a first level when said comparison data and said unit data are coincident with one another, and having a second level when said comparison data and said unit data supplied to said decision circuit are not coincident with one another;
a decision result register which is reset immediately after initiation of said test mode and which is set to a set level in response to said second level of said decision signal and holds a state until generation of a next register reset signal;
output control means for outputting, during said test mode, data held in said decision result register when an output enable signal is received by said output control means;
and
a control signal generating circuit which generates internal control signals, including said output enable signal, for controlling said memory cell array, said data input control means, said data register, said decision result register and said output control means;
wherein said control signal generating circuit controls an activation level and a nonactivation level of a test mode signal in accordance with a mutual level relation of a row address strobe signal, a column address strobe signal, a write enable signal and an output enable signal supplied from sources external to said semiconductor memory device, and which generates internal control signals including a register reset signal, a latch signal, a gate signal, a data input signal and a data output signal;
said semiconductor memory device further comprising:
a data-in buffer circuit which receives a 1-bit data from one of said outside sources in response to said data input signal,
a first selector which supplies said 1-bit data of said data-in buffer circuit to said memory cell array as said unit data of plural bits in response to said activation level of said test mode signal, and
a gate circuit which transmits said decision signal from said decision circuit to said decision result register in response to said gate signal;
said output control means comprising:
a second selector which selects and outputs said decision signal of said decision result register in response to said activation level of said test mode signal, and
a data-out buffer circuit which receives and outputs said decision signal supplied from said second selector in response to said data output signal;
wherein said decision result register is reset in response to said register reset signal;
and wherein said data register fetches and outputs said comparison data in response to said latch signal.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/527,761Filed 13 Sep 1995 · continuation
Priority: JP 5-0831909 Apr 1993
Granted: 30 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 29/38
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: response verification devices
G11C 29/40
Response verification devices: using compression techniques
G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…
G11C 29/46
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: test trigger logic