Synchronous memory allowing early read command in write to read transitions

A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of:

• initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data;
• and
• initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least a selected number of clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.

A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of:

• initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data;
• and
• initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least three clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, and initiating the read command after the second system clock cycle in response to selected command signals and the read latency number being one or two clock cycles, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.