Semiconductor memory device capable of operating at high speed and stably even under low power supply voltage

A semiconductor memory device, comprising:

• a memory cell array having a plurality of memory cells,
• said each memory cell including
• a flip-flop circuit having a first inverter having a first driver transistor of a first conductivity type and a first load element, and a second inverter having a second driver transistor of the first conductivity type and a second load element,
• a first access transistor of the first conductivity type connected to an output node of said first inverter, and
• a second access transistor of the first conductivity type connected to an output node of said second inverter;
• first and second bit lines connected to at least one of said memory cells through said first and second access transistors, respectively;
• bit line load means connected between said each bit line and a power source,
• said bit line load means including
• a depletion type MOS transistor connected between said bit line and the power source;
• a word line connected to gates of said first and second access transistors in common;
• write operation control means for controlling a potential of said word line to render said first and second access transistors conductive to transmit complementary potentials of said first and second bit lines to said memory cell when information is written in said memory cell;
• and
• read operation control means for controlling the potential of said word line to render said first and second access transistors conductive to transmit outputs of said first and second inverters to said first and second bit lines, respectively, and for setting a gate potential of said depletion type MOS transistor to a first potential when storage information of said memory cell is read out, and for setting the gate potential of said depletion type MOS transistor to a second potential when information of said memory cell is not read out.