Dynamic random access memory

A semiconductor memory device, comprising:

• a word line connected to a plurality of dynamic memory cells;
• a word line selecting circuit responsive to address signals, the word line selecting circuit including a precharge circuit and a discharge circuit serially connected between a node supplied with a word line driving potential and a terminal supplied with a ground potential, for generating a selection signal, the selection signal having the word line driving potential when the word line is not selected and the ground potential when the word line is selected, and outputting the selection signal via a series-connection node connecting said precharge circuit and said discharge circuit;
• a word line driving voltage source connected to said word line selecting circuit for supplying the word line driving potential, said word line driving voltage source being a voltage raising circuit for outputting a steady-level voltage as the word line driving potential during a first period in which said precharge circuit precharges the series-connection node and during a second period;
• and
• a word line driving circuit responsive to the selection signal, the word line driving circuit having a p-channel charging transistor and an n-channel discharging transistor, and being connected between the word line selecting circuit and the word line, and during the second period the word line driving circuit charging the word line to the word line driving potential with the p-channel charging transistor when the selection signal is at the ground potential and discharging the word line to the ground potential with the n-channel discharging transistor when the selection signal is at the word line driving potential.

A semiconductor memory device, comprising:

• a word line connected to a plurality of dynamic memory cells;
• a word line driving potential source for supplying a word line driving potential at an output node, said word line driving potential source being a voltage raising circuit for outputting a steady-level voltage as the word line driving potential;
• a word line selecting circuit having a first p-channel transistor, a first n-channel transistor, a second n-channel transistor, and a third n-channel transistor connected in series between the output node and a ground terminal, the word line selecting circuit providing a selection signal at a first connection node between the first p-channel transistor and the first n-channel transistor;
• and
• a word line driving circuit connected to the first connection node of the word line selection circuit, having a second p-channel transistor and a fourth n-channel transistor connected in series between the output node, supplied with the word line driving potential when the word line is selected, and the ground terminal, a second connection node between the second p-channel transistor and the fourth n-channel transistor being connected to the word line,
• wherein said word line driving potential source outputs the steady-level voltage for a first period in which said first p-channel transistor is in an ON state and a second period in which said second p-channel transistor is in an ON state.

A dynamic random access memory comprising:

• a dynamic memory cell having a transfer n-channel MOS transistor and a capacitive element for storing data which is connected to the transfer n-channel MOS transistor;
• a word line connected to a gate of the transfer n-channel MOS transistor of said dynamic memory cell;
• a charge pump circuit for receiving externally supplied power voltage and for generating an internal power supply voltage which is boosted up from the externally supplied power voltage, and outputting the internal power supply voltage as a steady-level voltage;
• a decoder circuit which receives address signals and having a first p-channel MOS transistor for receiving the steady-level voltage for generating a word line selecting signal;
• and
• a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, said word line driving circuit being provided in correspondence with said word line and having a second p-channel MOS transistor and a first n-channel MOS transistor, said second p-channel and MOS transistor having a source connected to a first node having the steady-level voltage, a drain connected to said word line and a gate which is controlled in accordance with the word line selecting signal, said first n-channel MOS transistor having a drain connected to said second p-channel MOS transistor, a source connected to a ground terminal and a gate which is controlled in accordance with the word line selecting signal,
• wherein said charge pump circuit outputs the steady-level voltage for a first period in which said first p-channel MOS transistor is in an ON state and a second period in which said second p-channel MOS transistor is in an on state.