Integrated circuit memory with multiplexed redundant column data path

An integrated circuit memory, comprising:

• a memory array comprising a plurality of memory cells organized in rows and columns;
• a redundant column of memory cells;
• a first data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for receiving data to the redundant column;
• a second data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to the redundant column;
• and
• a redundant multiplexer, coupled to the first and second data line portions, for determining which of the first or second data line portions is to provide the data to the redundant column.

An integrated circuit memory, comprising:

• a memory array comprising a plurality of memory cells organized in rows and columns;
• a plurality of global data lines, coupled to the memory array, for providing data to, and receiving data from, the memory array;
• a redundant column of memory cells;
• a first redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for providing data to and receiving data from the redundant column;
• a second redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to and receiving from data from the redundant column;
• and
• a redundant multiplexer, coupled to the first and second redundant data line portions, for determining which of the first or second redundant data line portions is to receive the data from, or provide the data to the redundant column.