Circuit and method for reading a memory cell that can store multiple bits of data

A method for reading a memory cell, comprising:

• storing in said memory cell one of a plurality of data levels, said plurality greater than two;
• associating each of said data levels with a different one of a plurality of signal levels;
• providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data level;
• generating an offset-reference value;
• generating a plurality of reference values that are each approximately equal to one of said signal levels;
• summing said offset-reference value with a first value of a group of values including said reference values and zero to generate a sum;
• comparing said signal level on said output terminal with said sum;
• adding said offset-reference value to a second value of said group of values to update said sum, said second value being within a range of said group of values, said range including the one of said group of values that is approximately equal to said signal level;
• and
• repeating said comparing and adding until said signal level is identified.

A sense circuit for reading a first memory cell that can store one of a first number of data levels, said first number greater than two, and that can provide on an output terminal one of said first number of current levels that each identify a corresponding one of said data levels, said one current level on said output terminal identifying said stored data level, said circuit comprising:

• a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and an output terminal;
• a successive approximation register having an input terminal coupled to said output terminal of said comparator, an output terminal that provides said stored data level, and a control output terminal;
• and
• a switch circuit having a control input terminal that is coupled to said control output terminal, an output terminal that is coupled to said second input terminal of said comparator, and at least one switch having a control terminal coupled to said control input terminal, a first path terminal coupled to said output terminal of said switch circuit, and a second path terminal;
• an offset-reference-current generator having an output terminal coupled to said output terminal of said switch circuit;
• and
• at least one reference-current generator that generates a reference current that is substantially equal to one of said current levels and that has an output terminal coupled to said second path terminal of said at least one switch.

A sense circuit for reading a memory cell that can store one of a plurality of data levels, said plurality greater than two, and that can provide on an output terminal one of a plurality of signal levels that each identify a corresponding one of the data levels, said one signal level on said output terminal identifying said stored data level, said circuit comprising:

• a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and a comparator output terminal;
• a successive approximation register having an input terminal coupled to said comparator output terminal, a register output terminal that provides said stored data level, and a register control output terminal;
• and
• a reference-signal generator having a control input terminal that is coupled to said register control output terminal, an output terminal that is coupled to said second input terminal of said comparator, an offset-reference generator that generates an offset-reference value, a plurality of reference generators that each generate a reference value that substantially equals one of said signal levels, and a switch circuit that is coupled to said control input terminal of said reference-signal generator, said switch circuit operable to provide on said output terminal of said reference-signal generator a sum of said offset reference value and one of said reference values selected by said successive approximation register.

A method for reading a memory cell, comprising:

• storing in said memory cell one of a plurality of data values, said plurality greater than two;
• associating each of said data values with a unique one of a plurality of signal levels;
• providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data value;
• generating an offset value;
• generating a plurality of reference values that are each approximately equal to one of said signal levels;
• summing said offset-reference value with a first one of said reference values to generate a sum;
• comparing said signal level on said output terminal of said memory cell with said sum;
• adding said offset value to a second one of said reference values, said second reference value being within a subgroup of said reference values that includes the reference value that is approximately equal to said signal level;
• and
• repeating said comparing and adding until said stored data level is determined.