Apparatus and method for reducing leakage current in a dynamic random access memory

A dynamic random access memory unit having a plurality of memory circuits, said memory circuits comprising:

• a sense amplifier;
• a first and a second bitline coupled to said sense amplifier;
• a storage cell unit including a storage cell capacitor and a pass transistor coupling said storage cell capacitor to said first bitline;
• a transistor coupled between said first and said second bitlines, said transistor having a gate terminal responsive to a bias voltage permitting charge to be transferred between said first and said second bitlines;
• and
• wherein said transfer of charge causes a voltage on said first bitline to rise and wherein said transfer of charge causes a bulk-to-source and a gate-to-source voltage of said pass transistor to become negative.

An semiconductor memory circuit for storing a charge state representative of a logic state, said memory circuit comprising:

• a sense amplifier;
• a bitline pair coupled to said sense amplifier, said sense amplifier amplifying differences in voltages between said bitlines when a control signal is applied thereto, said bitline pair being initialized to an equal potential;
• at least one storage cell coupled to each bitline of said bitline pair, said storage cell including;
• a storage cell capacitor, and
• a pass transistor coupled between said storage cell capacitor and said coupled bitline, said pass transistor providing a conducting path between said coupled bitline and said storage cell capacitor when a select signal is applied to a gate of said pass transistor;
• and
• a coupling transistor coupled between each bitline of said bitline pair, wherein a first signal applied tea gate terminal of said coupling transistor reduces a voltage difference between said bitline pair, said reduced voltage difference resulting in a negative base-to-source and gate-to-source voltage for said pass transistor when said pass transistor does not have said select signal applied thereto.