US 5,673,215 AGranted

Non-restoring fixed-point divider apparatus

AssigneeInternational Business Machines Corporation

InventorAlbert Suan-Wei Tsay

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Abstract

A divider for use in a data processing system and method of operation is disclosed The divider apparatus includes three 67-bit adders, coupled in parallel with one another for performing add or subtract functions, each adder being precharged during a first clock phase and executing selected functions during a second clock phase, which both occur during a single clock cycle. The first adder is connected to a first and second multiplexor, for selecting respective first and second operands. A third multiplexor, coupled to the second adder, is used to select a first operand for the second adder. Fourth and fifth multiplexors, which are coupled to the third adder, are used to select a respective first and second operand for the third adder. An adder operand select logic is coupled to the adders and the multiplexors for selecting whether to perform the add or subtract functions and for selecting which operands the multiplexors are to feed to their respective adders. An operand selection circuit is further added, which is coupled to the multiplexors and the adder operand select logic. The divider apparatus further comprising a remain quotient determination circuit coupled to the adders, and used for determining when a divide operation has been completed, what the divide result is, and whether there is a remainder quotient.

Claims13

Dependent claims

A fixed-point divider apparatus having a divider-input providing first, second, third, fourth, and fifth groups of input signals, said groups of input signals including a partial remainder and a divisor, wherein said fixed-point divider produces quotient bits as an output, said divider apparatus comprising:

first, second, and third adders, coupled in parallel one with another, for performing add or subtract functions, each adder being precharged during a first clock phase and executing one of said functions during a second clock phase, said first and second clock phases occurring during a single clock cycle;
first and second multiplexors, coupled to said divider-input and to said first adder, for selecting a respective first operand and a second operand for said first adder, which said first and second operands are selected from said first and second group of input signals, respectively;
a third multiplexor, coupled to said divider-input and to said second adder, for selecting a first operand for said second adder, which first operand for said second adder is selected from said third group of input signals;
fourth and fifth multiplexors, coupled to said divider-input and to said third adder, for selecting a respective first operand and a second operand for said third adder, which first and second third adder operands are selected from said fourth and fifth group of input signals, respectively;
an adder operand select logic circuit, coupled to said first, second, and third adders and said multiplexors, for selecting whether to perform the add or subtract function and for selecting which operands said first second third, fourth, and fifth multiplexors feed to said first, second, and third adders;
and
a remain quotient determination circuit, coupled to said first second, and third adders, for determining when a divide operation has been completed, what the divide result is in the form of said quotient bits, and whether there is a remainder quotient increment.

4 more elements

In a fixed-point divider apparatus having a plurality of adders including first, second, and third adders coupled in parallel, a plurality of multiplexors coupled to said plurality of adders, including first, second, third, fourth, and fifth multiplexors, an adder operand select logic coupled to said plurality of adders and to said plurality of multiplexors, an operand selection circuit coupled to said adder operand select logic and said plurality of multiplexors, and a remain quotient determination circuit coupled to said plurality of adders, a method of performing a fixed-point divide operation, comprising the following steps:

during a first phase of a clock cycle having a first and second phase, delivering first and second operands, selected from groups of input signals by said plurality of multiplexors, to said operand selection circuit for said plurality of adders;
during said first phase, precharging said plurality of adders and selecting respective first and second operands for each of said first, second, and third adders;
during said second phase, performing an adder operation on said selected first and second operands in said plurality of adders, wherein said adder operation yields first, second, and third adder results;
during a subsequent first phase, determining a next adder operation on at least one of said first, second, and third adder results;
during said subsequent first phase, generating adder results select signals for at least one of said plurality of multiplexors to select a desired one of said plurality of adders for performing said next adder operation;
during said subsequent first phase, selecting a correct result from said first, second, and third adder results;
generating a multi-bit quotient;
generating a next set of operands based on said selected correct result for said next adder operation;
and
during a subsequent second phase of a clock cycle, performing said next adder operation yielding another set of first, second, and third adder results.

7 more elements

Dependencies are inferred from the claim text.