Discrete cosine transform processor

A discrete cosine transform processor comprising:

• input means for receiving image data to be processed;
• storage means responsive to a read line for storing multiplication and accumulation values corresponding to the image data and transform matrix components for use in a discrete cosine transform arithmetic so that the same value is read from the same read line, wherein said storage means includes a first storage unit for storing the multiplication and accumulation values corresponding to even-numbered rows of the transform matrix components and a second storage unit for storing the multiplication and accumulation values corresponding to odd-numbered rows of the transform matrix components;
• decoding means for selecting the read line, in which the image data includes a plurality of bits representing address data, wherein said decoding means has a first decoder for accessing said first storage unit and a second decoder for accessing said second storage unit, wherein each one of the first decoder and the second decoder includes subdecoders for outputting three address values from two bits of the image data;
• accumulating means for accumulating the data read from said storage means;
• and
• output means for outputting a result of the accumulation processing as output data.