Voltage-controlled oscillator and PLL circuit exhibiting high-frequency band operation, linear frequency characteristics, and power-source variation immunity

A voltage-controlled oscillator for outputting an oscillating signal at a frequency corresponding to a control voltage applied thereto, comprising

• a plurality of delay circuits connected in a ring configuration and each providing a delay time varying with the applied control voltage, wherein
• each of said delay circuits comprises:
• a current source;
• and
• a differential pair of first and second inverting circuits each supplied with current from said current source, wherein said first inverting circuit comprises:
• a first FET supplied with the current from said current source to a source thereof;
• a first control element connected to a drain of said first FET to receive said control voltage applied thereto, said first control element having a linear current characteristic to the applied control voltage;
• and
• a first latch element connected in parallel to said first control element, said first latch element having a small resistance value when source-to-drain current flowing in said second FET is large and having a large resistance value when the source-to-drain current flowing in said second FET is small, and
• said second inverting circuit comprises:
• a second FET supplied with the current from said current source to a source thereof;
• a second control element connected to a drain of said second FET to receive said control voltage applied thereto, said second control element having a linear current characteristic to the applied control voltage, wherein
• an input signal to each of the delay circuits is inputted to respective gates of said first and second FETs and an output signal from each of the delay circuits is outputted from the respective drains of said first and second FETS;
• and
• a second latch element connected in parallel to said second control element, said second latch element having a small resistance value when source-to-drain current flowing in said first FET is large and having a large resistance value when the source-to-drain current flowing in said first FET is small,
• said first and second FETs are P-type or N-type FETs, and
• said first and second control elements are N-type or P-type FETs receiving said control voltage applied to respective gates thereof.