Substrate voltage supply control circuit for memory

Abstract

A substrate voltage supply control circuit for a memory which is capable of controlling substrate voltages having different voltage levels generated from a substrate voltage generating circuit included in the memory, so that different substrate voltages may be supplied to each circuit in memory depending on the state of each circuit, thereby reducing electrical power consumption in memory. The substrate voltage supply control circuit for a memory of the present invention includes first and second substrate voltage generating units for generating substrate voltages of high level and low level, respectively, according to a row address strobe signal, a power supply signal and an enable signal applied from the outside, and supplying the generated substrate voltage of high level to memory cells; a substrate voltage supply control unit for outputting first to fifth control signals and supplying the substrate voltages of high and low levels generated respectively by the first and second substrate voltage generating units, to each circuit inside of the memory according to the row address strobe signal and first to fourth address signals applied from the outside; and a substrate voltage selection unit for selecting substrate voltages of high and low levels generated respectively by the first and second substrate voltage generating unit according to the first to fifth control signals outputted from the substrate voltage supply control unit, and respectively supplying the selected voltages to memory peripheral circuits.

Dependencies are inferred from the claim text.