CMOS current mirror
AssigneeAdvanced Micro Devices, Inc.
InventorThomas J. Runaldue
Life of this patent
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Abstract
A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32,MP33), a variable input current source (I.sub.CS), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit 212. The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).
Claims18
A current mirror circuit for mirroring current in CMOS integrated circuit technology, comprising:
- a current mirror arrangement being formed of first and second P-channel MOS transistors (MP32,MP33), the gates of said first and second P-channel MOS transistors (MP32,MP33) being connected together and to the drain of said first P-channel MOS transistor (MP32), said first P-channel MOS transistor (MP32) having its source connected to a power supply potential and its drain connected to a first node (N31), said second P-channel MOS transistor (MP33) having its source connected to the power supply potential and its drain connected to a second node (N34);
- input current source means (I.sub.CS) for generating a variable current at said first node (N31);
- a first source follower transistor (MN34) having its gate connected to the first node (N31), its drain connected to the power supply potential, and its source connected to a third node (N33);
- a second source follower transistor (MP35) having its source connected to the second node (N34), its gate connected to the third node (N33), and its drain connected to a fourth node (N32);
- a current sinking transistor (MN31) having its gate and drain connected together and to the fourth node (N32) and its source connected to a ground potential;
- and
- load circuit means (212) interconnected between the third node (N33) and the ground potential for receiving current from said first source follower transistor (MN34).
In a differential current source driver (500) for use in a networking communication physical layer CMOS integrated circuit device, which includes a pair of identical current source driver circuits (510a, 510b), each of said pair of current source driver circuits comprising:
- a current mirror arrangement being formed of first and second P-channel MOS transistors (MP32,MP33), the gates of said first and second P-channel MOS transistors (MP32,MP33) being connected together and to the drain of said first P-channel MOS transistor (MP32), said first P-channel MOS transistor (MP32) having its source connected to a power supply potential and its drain connected to a first node (N31), said second P-channel MOS transistor (MP33) having its source connected to the power supply potential and its drain connected to a second node (N34);
- input current source means (I.sub.CS) for generating a variable current at said first node (N31);
- a first source follower transistor (MN34) having its gate connected to the first node (N31), its drain connected to the power supply potential, and its source connected to a third node (N33);
- a second source follower transistor (MP35) having its source connected to the second node (N34), its gate connected to the third node (N33), and its drain connected to a fourth node (N32);
- a current sinking transistor (MN31) having its gate and drain connected together and to the fourth node (N32) and its source connected to a ground potential;
- and
- load circuit means (212) interconnected between the third node (N33) and the ground potential for receiving current from said first source follower transistor (MN34).
Dependencies are inferred from the claim text.