Low noise output buffer circuit

An output buffer circuit, comprising:

• at least two output P-type MOS transistors, a source terminal of a first P-type MOS transistor of the at least two output P-type MOS transistors and a source terminal of a second P-type MOS transistor of the at least two output P-type MOS transistors being connected to a power supply and drain terminals of the first and second P-type MOS transistors being connected to an output pad;
• a first at least one resistive element, a first terminal of the first at least one resistive element being connected to a first gate terminal of the first P-type MOS transistor and a second terminal of the first at least one resistive element being connected to a second gate terminal of the second P-type MOS transistor;
• a first inverter having a first input terminal and a first output terminal, the first input terminal being connected to an input signal line and the first output terminal being connected to the first gate terminal of the first P-type MOS transistor;
• at least one charging P-type MOS transistor, the at least one charging transistor being a third P-type MOS transistor having a drain terminal connected to the second gate terminal of the second P-type MOS transistor, a source terminal of the third P-type MOS transistor being connected to the power supply and a gate terminal of the third P-type MOS transistor being connected to the input signal line;
• at least two output N-type MOS transistors, a source terminal of a first N-type MOS transistor of the at least two output N-type MOS transistors and a source terminal of a second N-type MOS transistor of the at least two output N-type MOS transistors being connected to the ground and drain terminals of the first and second N-type MOS transistors being connected to the output pad;
• a second at least one resistive element, a first terminal of the second at least one resistive element being connected to a first gate terminal of the first N-type MOS transistor and a second terminal of the second at least one resistive element being connected to a second gate terminal of the second N-type MOS transistor;
• a second inverter having a second input terminal and a second output terminal, the second input terminal being connected to the input signal line and the second output terminal being connected to the first gate terminal of the first N-type MOS transistor;
• and
• at least one charging N-type MOS transistor, the at least one charging transistor being a third N-type MOS transistor having a drain terminal connected to the second gate terminal of the second N-type MOS transistor, a source terminal of the third N-type MOS transistor being connected to the ground and a gate terminal of the third N-type MOS transistor being connected to the input signal line.

A 3-state output buffer circuit, comprising:

• at least two output P-type MOS transistors, a source terminal of a first P-type MOS transistor of the at least two output P-type MOS transistors and a source terminal of a second P-type MOS transistor of the at least two output P-type MOS transistors being connected to a power supply and drain terminals of the first and second P-type MOS transistors being connected to an output pad;
• a first at least one resistive element, a first terminal of the first at least one resistive element being connected to a first gate terminal of the first P-type MOS transistor and a second terminal of the first at least one resistive element being connected to a second gate terminal of the second P-type MOS transistor;
• a first inverter having a first input terminal and a first output terminal, the first input terminal being connected to a first input signal line and the first output terminal being connected to the first gate terminal of the first P-type MOS transistor;
• at least one charging P-type MOS transistor, the at least one charging transistor being a third P-type MOS transistor having a drain terminal connected to the second gate terminal of the second P-type MOS transistor, a source terminal of the third P-type MOS transistor being connected to the power supply and a gate terminal of the third P-type MOS transistor being connected to the first input signal line;
• at least two output N-type MOS transistors, a source terminal of a first N-type MOS transistor of the at least two output N-type MOS transistors and a source terminal of a second N-type MOS transistor of the at least two output N-type MOS transistors being connected to a ground and drain terminals of the first and second N-type MOS transistors being connected to the output pad;
• a second at least one resistive element, a first terminal of the second at least one resistive element being connected to a first gate terminal of the first N-type MOS transistor and a second terminal of the second at least one resistive element being connected to a second gate terminal of the second N-type MOS transistor;
• a second inverter having a second input terminal and a second output terminal, the second input terminal being connected to a second input signal line and the second output terminal being connected to the first gate terminal of the first N-type MOS transistor;
• and
• at least one charging N-type MOS transistor, the at least one charging transistor being a third N-type MOS transistor having a drain terminal connected to the second gate terminal of the second N-type MOS transistor, a source terminal of the third N-type MOS transistor being connected to the ground and a gate terminal of the third N-type MOS transistor being connected to the second input signal line.

An output buffer circuit, comprising:

• at least two output N-type MOS transistors, a source terminal of a first N-type MOS transistor of the at least two output N-type MOS transistors and a source terminal of a second N-type MOS transistor of the at least two N-type output MOS transistors being connected to a ground and drain terminals of the first and second N-type MOS transistors being connected to an output pad;
• at least one passive resistive element, a first terminal of one of the at least one passive resistive element being connected to a first gate terminal of the first N-type MOS transistor and a second terminal of the one of the at least one passive resistive element being connected to a second gate terminal of the second N-type MOS transistor;
• an inverter having an input terminal and an output terminal, the input terminal being connected to an input signal line and the output terminal being connected to the first gate terminal of the first N-type MOS transistor;
• and
• at least one charging N-type MOS transistor, the at least one charging transistor being a third N-type MOS transistor having a drain terminal connected to the second gate terminal of the second N-type MOS transistor, a source terminal of the third N-type MOS transistor being connected to the ground, a gate terminal of the third N-type MOS transistor being connected to the input signal line.