US 5,672,966 AGranted

High speed post-programming net packing method

AssigneeXilinx, Inc.

InventorsMikael Palczewski, David P. Schultz, F. Erich Goetting

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Abstract

A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws. The test is conducted simultaneously on a group of packed nets, wherein each group comprises a number of disjoint nets separated from one another by at least two MicroVia.TM. interconnects. A preferred packing method minimizes the number of net groups on a device for maximum test efficiency.

Claims10

Dependent claims

A method of verifying the connection layout of an array of conducting segments and programmable interconnects on an integrated circuit, said method comprising the steps of:

programming a selected set of said programmable interconnects to connect selected ones of said segments;
altering the voltage level at a first of said segments to a selected level;
measuring the voltage levels at a selected plurality of said segments;
verifying the accuracy of the connection layout by comparing the voltage levels at said plurality of segments to a set of voltage levels representing a desired connection layout for said selected plurality of segments,
wherein said altering step is performed simultaneously on a second plurality of segments, and wherein each of said second plurality of segments is separated by at least two programmable interconnects from said first segment and from any other one of said second plurality of segments.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/511,581Filed 4 Aug 1995 · continuation in part
Priority: 23 Jul 1992
Granted: 30 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 19/1736
By wiring, e.g. uncommitted logic arrays: in which the wiring can be modified
G01R 31/318519
Test of programmable logic devices [PLDs]: test of field programmable gate arrays [FPGA]
H03K 19/17764
Structural details of configuration resources: for reliability
H03K 19/1778
Arranged in matrix form: structural details for adapting physical parameters