US 5,672,911 AGranted

Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package

AssigneeLSI Logic Corporation

InventorsSadanand R. Patil, Tai-Yu Chou, Prabhansu Chakrabarti

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

Claims21

Dependent claims

A semiconductor device assembly, comprising:

a package substrate comprising a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers,
the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface,
the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors,
the first conductive pattern having a first plane and a third plane, the first plane connected to the plurality of first external connectors, and the third plane connected to the plurality of third external connectors,
the second conductive pattern having a second plane and a fourth plane, the second plane connected to the plurality of second external connectors, and the fourth plane connected to the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance;
and
a semiconductor die having core circuits and input-output circuits, said semiconductor die located on the top surface of said package substrate, said semiconductor die comprising:
a plurality of first power bond pads for the core circuits, the plurality of first power bond pads connected to the first plane,
a plurality of second power bond pads for the core circuits, the plurality of second power bond pads connected to the second plane,
a plurality of third power bond pads for the input-output circuits, the plurality of third power bond pads connected to the third plane,
a plurality of fourth power bond pads for the input-output circuits, the plurality of fourth power bond pads connected to the fourth plane, thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die, and
a plurality of signal bond pads, the plurality of signal bond pads connected to the plurality of signal external connectors of said package substrate.

9 more elements

A package substrate for a semiconductor die having core circuits, input-output circuits, a first plurality and a second plurality of power bond pads for the core circuits, a third plurality and a fourth plurality of power bond pads for the input-output circuits, and a plurality of signal bond pads, the package substrate comprising:

a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers;
the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface;
the top surface having a plurality of first traces for connecting to the first plurality of power bond pads, a plurality of second traces for connecting to the second plurality of power bond pads, a plurality of third traces for connecting to the third plurality of power bond pads, a plurality of fourth traces for connecting to the fourth plurality of power bond pads, and a plurality of signal traces for connecting to the plurality of signal bond pads;
the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors;
the first conductive pattern having a first plane and a third plane, the first plane connected to the plurality of first traces and the plurality of first external connectors, and the third plane connected to the plurality of third traces and the plurality of third external connectors;
the second conductive pattern having a second plane and a fourth plane, the second plane connected to the plurality of second traces and the plurality of second external connectors, and the fourth plane connected to the plurality of fourth traces and the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die;
and
the plurality of signal traces connected to the plurality of signal external connectors.

5 more elements

A semiconductor device assembly, comprising:

a semiconductor die having core circuits and input-output circuits, said semiconductor die having
at least one first power bond pad for the core circuits,
at least one second power bond pad for the core circuits,
at least one third power bond pad for the input-output circuits,
at least one fourth power bond pad for the input-output circuits, and
a plurality of signal bond pads;
a package substrate having first, second, third and fourth conductive patterns, first, second and third dielectric layers, at least one each of a first, second, third and fourth top vias, at least one each of a first, second, third and fourth bottom vias, a plurality of signal vias, at least one each of a first, second, third and fourth external connectors, a plurality of signal external connectors, and a top surface,
the first dielectric layer disposed between the first and second conductive patterns, the second dielectric layer disposed between the second and third conductive patterns, and the third dielectric layer disposed between the third and fourth conductive patterns,
the top surface of said package substrate defined by the first dielectric layer and the first conductive pattern disposed thereon, said semiconductor die located adjacent to the top surface;
the first conductive pattern of said package substrate comprising
an at least first top trace for connecting the at least one first power bond pad to the at least one first top via,
an at least second top trace for connecting the at least one second power bond pad, to the at least one second top via,
an at least third top trace for connecting the at least one third bond pad to the at least one third top via,
an at least fourth top trace for connecting the at least one fourth power bond pad to the at least one fourth top via, and
a plurality of top signal traces for connecting the plurality of signal bond pads to the plurality of signal vias;
the second conductive pattern of said package substrate comprising at least one each of a first and third planes, the at least one first plane connected to the at least one first top via and the at least one first bottom via, and the at least one third plane connected to the at least one third top via and the at least one third bottom via;
the third conductive pattern of said package substrate comprising at least one each of a second and fourth planes,
the at least one second plane connected to the at least one second top via and the at least one second bottom via, and the at least one fourth plane connected to the at least one fourth top via and the at least one fourth bottom via,
the first and second planes positioned in a biplanar relationship for forming an electrical capacitance,
the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance;
and
the fourth conductive pattern of said package substrate comprising
an at least one first bottom trace for connecting the at least one first bottom via to the at least one first external connector,
an at least one second bottom trace for connecting the at least one second bottom via to the at least one second external connector,
an at least one third bottom trace for connecting the at least one third bottom via to the at one third external connector,
an at least one fourth bottom trace for connecting the at least one fourth bottom via to the at least one fourth external connector, and
a plurality of bottom signal traces for connecting the plurality of signal vias to the plurality of signal external connectors,
thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die.

25 more elements

Dependencies are inferred from the claim text.