Insulated gate field effect transistor with an anodic oxidized gate electrode
OwnerToshimitsu Konuma, Akira Sugawara +1inventors
InventorsToshimitsu Konuma, Akira Sugawara, Takahiro Tsuji
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Abstract
A thin-film transistor (TFT) comprising an active region provided on a substrate and a gate electrode on the active region. A porous anodic oxide film is provided on the sides and top of the gate electrode where the lateral thickness of the anodic oxide provided on the side surface is larger than the vertical thickness of the anodic oxide provided on the top surface or where a first anodic oxide is provided on both the top and side surfaces and a second anodic oxide is provided on the side surfaces wherein the first anodic oxide is interposed between the second anodic oxide and the side surfaces of the gate electrode.
Claims10
A transistor comprising:
- an active region comprising a semiconductor material;
- a gate electrode provided over said active region, said gate electrode comprising an anodizable material;
- and
- a first anodic oxide of the material of said gate electrode provided on a side surface and a top surface of said gate electrode;
- and
- a second anodic oxide of the material of said gate electrode provided adjacent to the side surface of said gate electrode with said first anodic oxide interposed therebetween,
- wherein said second anodic oxide is more porous than said first anodic oxide.
A thin film transistor formed on a substrate comprising:
- a semiconductor layer having at least source, drain and channel regions;
- a gate electrode adjacent to said channel region with a gate insulating layer therebetween;
- an insulating layer comprising an oxide of a material of said gate electrode formed on an upper surface and a side surface of said gate electrode;
- and
- a first offset region formed between said channel region and said source region and a second offset region formed between said channel region and said drain region,
- wherein a lateral thickness of said insulating layer on the side surface of said gate electrode is larger than a vertical thickness of said insulating layer on the upper surface of the gate electrode, and boundaries between said first offset region and said source region and between said second offset region and said drain region are substantially aligned with outer side edges of said insulating layer.
Dependencies are inferred from the claim text.