Thin-film transistor and thin-film transistor array
AssigneeNEC Corporation
InventorKenichi Nakamura
Life of this patent
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Abstract
An active layer is sandwiched between a first gate electrode and a second gate electrode, and an offset region is disposed in overlying and underlying relation to a third gate electrode and a fourth gate electrode, respectively, resulting in a double-gate structure that is effective to produce a large ON current and a low leakage current. Storage capacitances for suppressing a reduction in a pixel potential are formed between a transparent pixel electrode and a third storage capacitance electrode, between the third storage capacitance electrode and a second storage capacitance electrode, and between the second storage capacitance electrode and a first storage capacitance electrode. Large storage capacitances are thus formed in a small area.
Claims5
A thin-film transistor comprising:
- a semiconductor layer having an active layer and source and drain regions;
- a first gate insulating film disposed under said semiconductor layer;
- a first gate electrode disposed under said first gate insulating film in underlying relation to said active layer;
- a second gate insulating film disposed over said semiconductor layer;
- a second gate electrode disposed over said second gate insulating film in overlying relation to said active layer;
- a first interlayer insulating film disposed over said second gate insulating film;
- an offset region disposed between said active layer and said source and drain regions and comprising a semiconductor layer having a low impurity concentration;
- a third gate electrode electrically connected to said first gate electrode in overlapping relation to at least said offset region, said third gate electrode being disposed out of overlapping relation to said source and, drain regions;
- and
- a fourth gate electrode electrically connected to said second gate electrode in overlapping relation to at least said offset region, said fourth gate electrode being disposed out of overlapping relation to said source and drain regions;
- wherein said first gate insulating film has a portion which is disposed between said semiconductor layer and said first gate electrode and has a film thickness d1, and said first gate insulating film has a portion which is disposed between said semiconductor layer and said third gate electrode and has a film thickness d3, said film thicknesses d1, d3 satisfying the relationship:
- d3>d1;
- and
- said second gate insulating film has a portion which is disposed between said semiconductor layer and said second gate electrode and has a film thickness d2, and said second gate insulating film and said first interlayer insulating film have portions which are disposed between said semiconductor layer and said fourth gate electrode and have a film thickness d4, said film thicknesses d2, d4 satisfying the relationship:
- d4>d2.
Dependencies are inferred from the claim text.