Method of manufacturing a novel static memory cell having a tunnel diode

A method of manufacturing a static memory cell, comprising:

• providing a p-type substrate having an average p-type dopant concentration of at least about 1.times.10.sup.16 ions/cm.sup.3 ;
• forming a buried n-type layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 ;
• forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a gate, a memory node having an average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and a digit line node having an average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and wherein the memory node is closer to the buried n-type layer than the digit line node;
• and
• forming a p-type region in junction with the memory node to define a tunnel diode between the p-type region and the memory node.

A method of manufacturing a static memory cell, comprising:

• providing an n-type substrate having an average n-type dopant concentration of at least about 1.times.10.sup.16 ions/cm.sup.3 ;
• forming a buried p-type layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 ;
• forming a p-channel transistor relative to the substrate over the buried p-type layer, the p-channel transistor having a gate, a memory node having an average p-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and a digit line node having an average p-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and wherein the memory node is closer to the buried p-type layer than the digit line node;
• and
• forming an n-type region in junction with the memory node to define a tunnel diode between the n-type region and the memory node.