Process for fabricating capacitor cells in dynamic random access memory (DRAM) chips

A process for fabricating a capacitor cell in a DRAM chip, comprising the steps of:

• forming on a substrate a field oxide layer, a transistor cell, and an insulation layer, the insulation layer having a contact opening formed therethrough;
• forming a stacked structure including a plurality of first polysilicon layers and insulation spacers alternately formed on the insulation layer, the bottom-most polysilicon layer in the stacked structure being implanted with impurities to increase conductivity thereof and coupled to the substrate via the contact opening;
• etching through the plurality of first polysilicon layers and insulation spacers in the stacked structure until reaching the bottom-most polysilicon layer so as to form an opening therethrough;
• wet etching away portions of the plurality of first polysilicon layers that are exposed on the inner wall of the opening so as to form a plurality of grooves on the inner wall of the opening;
• forming a second polysilicon layer to the inner wall of the opening so as to cover the plurality of grooves formed thereon;
• defining a range for the capacitor cell by etching the second polysilicon layer and the plurality of first polysilicon layers and insulation spacers in the stacked structure, whereby part of the second polysilicon layer that is connected to each of the first polysilicon layers in the stacked structure serves as a bottom plate for the capacitor cell;
• removing each of the insulation spacers in the stacked structure while retaining the bottom plate;
• heat treating to form a dielectric layer covering the bottom plate and also to allow the impurities in the bottom-most polysilicon layer in the stacked structure to be diffused through the contact opening into the substrate so as to form a contact region on the substrate;
• and
• forming a third polysilicon layer covering the dielectric layer to serve as a top plate for the capacitor cell.