Field effect transistor having impurity regions of different depths and manufacturing method thereof

A method of manufacturing a semiconductor device including a memory cell array region and a peripheral circuit region, each of said memory cell array region and said peripheral circuit region having a field effect transistor, comprising the steps of:

• forming a first gate electrode on a semiconductor substrate in said memory cell array region, and a second gate electrode on the semiconductor substrate in said peripheral circuit region;
• forming a first sidewall insulation film on sidewalls of said first gate electrode in said memory cell array region and a second sidewall insulation film on sidewalls of said second gate electrode in said peripheral circuit region;
• forming a first impurity region in the memory cell array region and a second impurity region in the peripheral circuit region by implanting impurity ions with said first and second sidewall insulation films as a mask;
• forming a conductive layer and a first insulation film on said first impurity region and said first sidewall insulation film in said memory cell array region, and on said second impurity region and said second sidewall insulation film in said peripheral circuit region, and patterning said conductive layer and said first insulation film into a configuration to form a first insulator layer on a first conductor layer in said memory cell array region and a second insulator layer on a second conductor layer in said peripheral circuit region;
• forming a second insulation film all over said semiconductor substrate and anisotropically etching the second insulation film to form a third sidewall insulation film on a sidewall of said first conductor layer and on a portion of said first sidewall insulation film formed on sidewalls of said first gate electrode in said memory cell array region, and a fourth sidewall insulation film on a sidewall of said second conductor layer and on a portion of said second sidewall insulation film formed on sidewalls of said second gate electrode in said peripheral circuit region;
• and
• forming a third impurity region in said memory cell array region and a fourth impurity region in said peripheral circuit region by diffusing the impurities introduced in a third conductive layer, formed on said third sidewall insulation film and on the semiconductor substrate, into said semiconductor substrate by heat treatment.