Three-dimensional complementary field effect transistor process

A method comprising:

• growing a region of thermal oxide in a semiconductor material so as to form a step in an upper surface of said semiconductor material, said step having a sidewall surface, wherein the upper surface comprises a first substantially lateral and planar surface, the sidewall surface, and a second substantially lateral and planar surface, the first surface being laterally and vertically displaced with respect to the second surface;
• removing the thermal oxide from said sidewall surface;
• forming a gate insulating layer on said sidewall surface;
• forming a gate of a transistor over said gate insulating layer such that a channel region of said transistor is disposed in said semiconductor material at said sidewall surface;
• forming a source region of the transistor in the semiconductor material at the second surface;
• and
• forming a drain region of the transistor in the semiconductor material at the first surface, wherein said drain region is bounded in a lateral dimension by said source region of the transistor.

A method, comprising:

• growing a region of thermal oxide into a semiconductor material and thereby forming a depression into an upper surface of the semiconductor material, the depression having:
• substantially parallel first and second sidewall surfaces formed in the semiconductor material,
• substantially parallel third and fourth sidewall surfaces formed in the semiconductor material, wherein said first and said second sidewall surfaces have a steeper slope than said third and said fourth sidewall surfaces, and
• a bottom surface;
• removing the thermal oxide from the depression and from the sidewall surfaces;
• forming a gate oxide on the first and second sidewall surfaces;
• forming a first gate over the gate oxide on the first sidewall surface and forming a second gate over the gate oxide on the second sidewall surface;
• forming a first source region and a second source region outside the depression;
• and
• using the first and second gates as masks to form a drain region into the bottom surface, wherein said drain region is confined in a lateral dimension between said first and said second source regions.

A method, comprising:

• shaping multiple nitride layers on a semiconductor material;
• performing a thermal oxidation step to form a depression into the semiconductor material, the depression having a first sloping sidewall surface and a second sloping sidewall surface, wherein said first sloping sidewall surface has a steeper slope than said second sloping sidewall surface;
• removing thermal oxide from the depression and from the sidewall surfaces and forming a gate oxide on the sloping sidewall surfaces;
• and
• forming a conductive layer over the depression and removing selected portions of the conductive layer such that gate structures remain along the first sloping sidewall surface but do not remain along the second sloping sidewall surface.

A method for forming a channel region of a field effect transistor, comprising:

• forming a thin nitride layer overlying a semiconductor material;
• forming a thick nitride layer which is separated from the thin nitride layer;
• growing a thermal oxide into said semiconductor material using the thin and thick nitride layers as an oxidation mask to form a depression in said semiconductor material having a first sidewall surface and a second sidewall surface;
• implanting first impurities into portions of said semiconductor material to form a doped region in said first and said second sidewall surfaces;
• etching said thermal oxide from said depression and said first and said second sidewall surfaces;
• implanting second impurities into said semiconductor material to form a lightly doped drain region in a bottom surface of said depression;
• using said first sidewall surface of the depression as said channel region of said field effect transistor;
• and
• implanting third impurities into said semiconductor material to form a heavily doped source region and to form a heavily doped drain region confined within said lightly doped drain region.

A method comprising:

• forming a thin nitride layer vertically displaced above a semiconductor material;
• forming a thick nitride layer which is separated in a vertical dimension from said thin nitride layer;
• shaping said thin and thick nitride layers;
• performing a thermal oxidation step to form a depression into said semiconductor material so as to form a first step and a second step in an upper surface of said semiconductor material, said first and said second steps each having a sloping sidewall surface, wherein said sloping sidewall surface of said first step is steeper than said sloping sidewall surface of said second step;
• removing thermal oxide from the depression and said sloping sidewall surfaces of said first and said second steps and forming a gate insulating layer on said sloping sidewall surfaces of said first and said second steps;
• and
• forming a gate of a transistor over said gate insulating layer such that a channel region of said transistor is disposed in said semiconductor material at said sloping sidewall surface of said first step.