Direct memory access acceleration device for use in a data processing system

A device for increasing a data transfer rate between a system bus and an input/output adapter during a direct memory access operation, comprising:

• an address counter coupled to the system bus for maintaining an address of a system memory, wherein a host processor loads said address counter with an initial address, wherein said initial address is incremented during the direct memory access operation;
• a byte counter coupled to the system bus for counting data to be transferred during the direct access memory operation;
• an address decode circuit coupled to the system bus for decoding control signals in order to select the input/output adapter for the direct memory access operation;
• receive and transmit state machines coupled to the system bus and the input/output adapter, for generating the control signals during the direct memory access operation, said receive and transmit state machines being programmed to read and write data in parallel between the system bus and the input/output adapter;
• a control/status register coupled to the system bus, for enabling said receive and transmit state machines in response to a request by the host processor,
• a multiplexer coupled to the system bus, for selecting plurality of control signals to be driven to the input/output adapter;
• a register coupled to the system bus, for holding a bus identification number assigned to the input/output adapter;
• an arbitration decode circuit coupled to the system bus, for comparing said bus identification number with a number received from the system bus;
• and
• data storage means coupled to said state machines, for providing temporal delay to stabilize data in response to the control signals from said receive and transmit state machines.

A method for increasing a data transfer rate between a system bus and an input/output adapter during a direct memory access receive operation, comprising:

• starting a receive state machine, wherein a first control signal initiates data transfer from the input/output adapter to the system bus;
• reading a data unit from the input/output adapter by the receive state machine;
• writing said data unit to the system bus while simultaneously initializing addressing for reading another data unit subsequent to said data unit being written to the system bus from the input/output adapter;
• sequentially repeating said step of reading a data unit units from the input/output adapter and the step of writing of said data units to the system bus while simultaneously initializing addressing for reading another data unit subsequent to said data unit being written to the system bus from the input/output adapter;
• and
• stopping said receive state machine, wherein a second control signal concludes the data transfer from the input/output adapter to the system bus.