Technique for software to identify features implemented in a processor

A processor for providing identification information pertaining to itself when queried by a processor identification instruction comprising:

• a control unit for controlling said processor in response to said processor identification instruction;
• a first register containing a first data field which identifies a higher-level attribute of said processor, said first register also containing a second data field and a third data field, said first register coupled to said control unit;
• at least one second register containing information pertaining to identification of a source of said processor, wherein said second data field contained in said first register identifies a number of said second register or registers present, said second register or registers coupled to said control unit;
• at least one third register containing information which identifies a lower-level attribute of said processor, wherein said third data field contained in said first register identifies a number of said third register or registers present, said third register or registers coupled to said control unit.

A computer system coupled to receive and respond to computer instructions from a program routine comprising:

• a processing unit for receiving, decoding and executing said computer instructions and in which one of said instructions is an identification instruction for identifying a processing characteristic of said computer system;
• a first register containing a first data field which identifies a higher-level attribute of said processing characteristic of said computer system, said first register also containing a second data field and a third data field, said first register coupled to said processing unit;
• at least one second register containing information pertaining to identification of a source of said processing characteristic of said computer system, wherein said second data field contained in said first register identifies a number of said second register or registers present, said second register or registers coupled to said processing unit;
• at least one third register containing information which identifies a lower-level attribute of said processing characteristic of said computer system, wherein said third data field contained in said first register identifies a number of said third register or registers present, said third register or registers coupled to said processing unit
• wherein when said identification instruction is executed, information pertaining to said processing characteristic of said computer system is read.

In a processor which includes a decoder for decoding instructions and a control unit for generating control signals for controlling said processor, a method of providing identification information pertaining to said processor when queried by a processor identification instruction, comprising the steps of:

• having a first data field in a first register to identify a higher-level attribute of said processor;
• having a second data field and a third data field also in said first register;
• having information pertaining to identification of a source of said processor in at least one second register, wherein said second data field of said first register identifies a number of said second register or registers present;
• having information which identifies a lower-level attribute of said processor in at least one third register, wherein said third data field of said first register identifies a number of said third register or registers present;
• executing said processor identification instruction to access and read said first register;
• wherein reading said data fields of said first register identifies said higher-level attribute and numbers of said second and third registers present.

In a computer system having a processor as a central processing unit and in which said processor includes a decoder for decoding instructions and a control unit for generating control signals for controlling said processor, a method of providing identification information pertaining to said processor when queried by a processor identification instruction, comprising the steps of:

• having a first data field in a first register to identify a higher-level attribute of said processor;
• having a second data field and a third data field also in said first register;
• having information pertaining to identification of a source of said processor in at least one second register, wherein said second data field of said first register identifies a number of said second register or registers present;
• having information which identifies a lower-level attribute of said processor in at least one third register, wherein said third data field of said first register identifies a number of said third register or registers present;
• executing said processor identification instruction to access and read said first, second and third data fields in said first register;
• wherein reading said data fields of said first register identifies said higher-level attribute and numbers of said second and third registers present.