Microprocessor controlled apparatus

A method of transmitting data information from a first electrical device to a second electrical device comprising steps of:

• sending signals from the first device to the second device through a sub-set of first device dedicated address lines that convey only address information, the sub-set being less than a total number of the first device address lines;
• maintaining the signals constant on all of the individual sub-set lines for a predetermined period of time while signals on other address lines of the first device change, wherein the signals on the sub-set lines are held at a constant level over the predetermined period of time to permit the signals to be written into the second device;
• and, in the second device,
• interpreting the signals that are written into the device as data information, and not as address information.

In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising:

• coupling a sub-set of the signal line set to the at least one data signal line;
• executing, with the digital data processor, a plurality of instructions;
• and
• during the execution of the plurality of instructions, triggering the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.

A data processing system, comprising:

• a memory comprised of a plurality of addressable storage locations for storing executable instructions;
• a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations;
• and
• at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set;
• wherein
• said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is triggered to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.

In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising:

• coupling a sub-set of the signal line set to the at least one data signal line;
• executing, with the digital data processor, a plurality of instructions;
• and
• during the execution of the plurality of instructions, causing the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.

A data processing system, comprising:

• a memory comprised of a plurality of addressable storage locations for storing executable instructions;
• a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations;
• and
• at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set;
• wherein
• said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is caused to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.