US 5,671,432 AGranted

Programmable array I/O-routing resource

AssigneesInternational Business Machines Corporation, Cadence Design Systems, Inc.

InventorsAllan Robert Bertolet, Kenneth Ferguson, Scott Whitney Gould, Eric Ernest Millham, Ronald Raymond Palmer, Brian Worth, Terrance John Zittritsch

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Abstract

A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Claims38

Dependent claims

A programmable array having a plurality of programmable logic cells arrayed therein, said programmable array further comprising:

a programmable interconnect network, the programmable interconnect network comprising a first plurality of buses wherein selected buses in the first plurality of buses are connectable to ones of the plurality of logic cells, the first plurality of buses including a plurality of switches, at least some switches of the plurality of switches for programmably providing signals between buses of the first plurality of buses;
and
a first I/O interface associated with a corresponding one of the plurality of logic cells, the first I/O interface comprising:
a data output path for carrying array output signals to an I/O terminal corresponding to the first I/O interface;
a data input path for carrying array input signals from the I/O terminal corresponding to the first I/O interface;
a first multiplexer having an output connected to said data output path, said first multiplexer further having a plurality of inputs;
a second multiplexer having an input connected to said data input path, said second multiplexer further having a plurality of outputs;
and
first and second I/O signal buses, the first I/O signal bus being connected between one of the switches of the first plurality of buses and one of the plurality of inputs of the first multiplexer, the second I/O signal bus being connected between one of the switches of the first plurality of buses and one of the plurality of outputs of the second multiplexer.

6 more elements

An I/O and interconnect system for a programmable array having a plurality of programmable logic cells, the I/O and interconnect system comprising:

an I/O terminal;
an I/O interface corresponding to said I/O terminal, said I/O interface including a first multiplexer connected thereto;
a general interconnect network for interconnecting the plurality of programmable logic cells, the general interconnect network comprising a first plurality of parallel interconnect buses, the first plurality of parallel interconnect buses including a first extended bus connected to the first multiplexer of the I/O interface;
and
a plurality of perimeter buses, said plurality of perimeter buses running along a perimeter of the array, at least one of the plurality of perimeter buses being programmably connectable to the extended bus of the first plurality of parallel interconnect buses.

2 more elements

A programmable array having a plurality of logic cells arranged in rows and columns therein including a plurality of perimeter logic cells, and a programmable interconnect network for interconnecting logic cells of the plurality of logic cells, the programmable interconnect network comprising a plurality of buses, at least some of the plurality of buses being generally associated with, and connectable to, respective ones of the plurality of logic cells, said programmable array further comprising:

a routing network disposed at the perimeter of the array, said routing network comprising a plurality of buses;
a plurality of I/O interfaces about the perimeter of the array, such that each of a portion of the plurality of perimeter logic cells has two I/O interfaces corresponding thereto;
a plurality of first conductors for programmably connecting at least some of the plurality of I/O interfaces to corresponding logic cells about the perimeter of the array;
a plurality of second conductors for programmably connecting the at least some of the plurality of I/O interfaces to corresponding ones of the plurality of buses of the programmable interconnect network;
and
a plurality of programmable connections for programmably connecting at least some of the plurality of buses of the routing network to at least some of the plurality of second conductors.

3 more elements

Dependencies are inferred from the claim text.