US 5,671,421 A · Serial interrupt bus protocol

Abstract

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

Claims19

Dependent claims

A computer system comprising:

a central processing unit (CPU) for executing an interrupt service routine in response to an interrupt pending signal;
a first interrupt controller coupled to provide said interrupt pending signal to said CPU in response to any one of a plurality of potential interrupt request signals;
a serial interrupt controller coupled to said first interrupt controller, said serial interrupt controller generating an appropriate one of said plurality of potential interrupt request signals corresponding to a received serial interrupt request signal;
and
a first plurality of serial interrupt peripherals interconnected and in communication with said serial interrupt controller, wherein each one of said first plurality of serial interrupt peripherals may request one or more of said plurality of potential interrupt request signals to be generated by said serial interrupt controller, each of said first plurality of serial interrupt peripherals including protocol logic configured to serially propagate said serial interrupt request signal to said serial interrupt controller.

2 more elements

A peripheral for use in a computer system wherein said computer system includes a central processing unit (CPU), a first interrupt controller for notifying a said CPU of a pending interrupt in response to one of a plurality of potential interrupt request signals, and a serial interrupt controller for providing said interrupt request signals to said first interrupt controller in response to a received serial interrupt request signal, said peripheral comprising:

serial interrupt protocol logic for communicating with a serial interrupt bus;
a serial interrupt input coupled to said serial interrupt protocol logic, said serial interrupt input coupling said peripheral to said serial interrupt bus for receiving serial interrupt request signals;
and
a serial interrupt output coupled to said serial interrupt protocol logic, said serial interrupt output coupling said peripheral to said serial interrupt bus for conveying serial interrupt request signals over said serial interrupt bus,
wherein said serial interrupt protocol logic controls said serial interrupt output such that a serial interrupt request signal corresponding to any one of said plurality of potential interrupt requests may be received at said serial interrupt input and propagated through said serial interrupt output.

2 more elements

Dependencies are inferred from the claim text.

Serial interrupt bus protocol

Life of this patent

Serial interrupt bus protocol

Life of this patent

Abstract

Claims19