Apparatus for efficiently accessing graphic data for rendering on a display

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising:

• a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising:
• a plurality of memory units for storing information representing said geometric primitive wherein information associated with each vertex of said geometric primitive is stored in a separate memory unit;
• a mathematical processing circuit processing said information representing said geometric primitive in a predetermined vertex ordering to provide display information regarding said geometric primitive;
• multiplexing circuitry coupled to said plurality of memory units and coupled to said mathematical processing circuit, said multiplexing circuitry simultaneously providing said information representing said geometric primitive from said plurality of memory units to said mathematical unit in said predetermined vertex ordering;
• and
• vertex order determining circuitry determining a vertex ordering of said geometric primitive and generating output pointers indicative of said vertex ordering, said vertex order determining circuitry coupled to receive comparison signals indicating results of comparisons of parameters associated with pairs of said vertices of said geometric primitive.

In a computer controlled graphics system including a display displaying computer generated images and a memory unit storing information representing geometric primitives, an apparatus for rendering said geometric primitives onto said display, said apparatus comprising:

• a plurality of processors coupled to a common instruction bus according to a SIMD architecture, each processor simultaneously processing a separate geometric primitive, each processor further comprising:
• a first circuit determining slopes based on said information associated with said plurality of vertices of said geometric primitive, each slope associated with an edge of said geometric primitive, said first circuit processing said information associated with said plurality of vertices in a predetermined vertex order, said first circuit coupled to a plurality of signal lines for receiving said information;
• a plurality of memories for storing said information associated with said plurality of vertices, each memory for storing information associated with a separate vertex of said geometric primitive and each memory having a separate output line;
• multiplexing circuitry coupled to said plurality of memories and coupled to said first circuit for intercoupling an output line of each memory to an individual signal line of said plurality of signal lines coupled to said first circuit wherein said multiplexing circuitry simultaneously supplies said information associated with said plurality of vertices from said plurality of memories to said first circuit in said predetermined vertex order;
• a second circuit generating comparison results of screen coordinate values between pairs of vertices of said geometric primitive;
• and
• a third circuit ordering said plurality of vertices of said geometric primitive according to said predetermined vertex order, said third circuit coupled to receive said comparison results from said second circuit and coupled to control said multiplexing circuitry.