Programmable bus interface unit data path

A data path interface system embodied in a field programmable gate array, for data transfers between a processor operating on a first clock rate and first protocol, and a system bus operating on a second clock rate and second protocol, said interface system comprising:

• (a) address register means for holding addresses of data being transferred from said process or to said system bus or from said system bus to said processor;
• (b) message buffer means for holding messages being transferred from said processor to said system bus, each said message including four words of "X" bits each;
• (c) data queue means for holding data received from main memory and for routing messages transferred from said system bus and destined for said processor, including:
• (c1) means to transfer single word messages to said processor at the said processor clock rate;
• (c2) means to transfer single word, double word and four-word blocks of memory data to said processor at the processor clock rate;
• (d) transfer logic box means for holding (i) N request messages to said processor and (ii) N acknowledge messages to said processor, including:
• (d1) means to transfer to said processor, each one of said N request and N acknowledge messages to said data queue means one word at a time at the processor clock rate for subsequent transfer to said processor;
• (e) control logic means regulating the transfer times of addresses, data, and messages flowing through said address registers, through said message buffer means, through said data queue means, and through said transfer logic box means;
• (f) said system bus means operating at said second clock rate and second protocol for connecting said data path interface system to an external main memory, I/O module, and other external modules.