Method for hierarchic logic verification of VLSI circuits

A method for hierarchic logic verification of VLSI circuits, a hierarchic layout circuit acquired from a physical layout of a VLSI circuit using an extraction procedure being compared to a hierarchic logic plan circuit defined by a logic plan, the layout circuit and the logic plan circuit having sub-circuits, comprising the steps of:

• canceling terminals of a respective sub-circuit of the sub-circuits that are not connected to any component of the respective sub-circuit within this sub-circuit, or are not connected to any occurrence of a lower-ranking sub-circuit that belongs to at least one next-lower hierarchy level;
• combining terminals of a respective sub-circuit of the subcircuits that are externally connected to one another in all occurrences of the respective sub-circuit to form a common terminal, whereby this ensues across all hierarchy levels;
• and
• canceling terminals of a respective sub-circuit of the sub-circuits that do not have an external connection to at least one component of another sub-circuit of the sub-circuits in any occurrence of this sub-circuit as external terminal on the respective hierarchy level, wherein the layout circuit as well as the hierarchic logic plan circuit are transformed such that a number of terminals of sub-circuits of each hierarchy level is minimal;
• forming pairs of potentially equivalent sub-circuits in that corresponding sub-circuits with a common name are sought in the layout circuit and in the logic plan circuit and are only allocated to one another for sub-circuits having an identical number of terminals;
• replacing occurrences of sub-circuits, to which a partner in the respectively other circuit is allocated, by a macro component that cannot be further detailed, insofar as at least all terminals of both occurrences of sub-circuits are completely allocated to one another;
• partially expanding occurrences of sub-circuits, to which no partner in the respectively other circuit is allocated, by switching to a lower hierarchy level until at least one occurrence of a sub-circuit is again present for which a partner in the respectively other circuit exists with allocated terminals, and replacing the respective occurrence of the respective lower-ranking sub-circuit by a respective macro component;
• further partially expanding occurrences of sub-circuits to which a partner in the respectively other circuit is allocated and wherein all terminals of both occurrences cannot be allocated to one another, or suppressing comparison of the higher-ranking circuit parts;
• and
• further partially expanding occurrences of sub-circuits that do not occur an identical number of times in both circuits until a plurality of occurrences of all sub-circuits respectively corresponding to one another coincides, wherein internal hierarchies of a pair of potentially equivalent sub-circuits are reshaped into isomorphic hierarchies.

A method for hierarchic logic verification of VLSI circuits, a hierarchic layout circuit acquired from a physical layout of a VLSI circuit using an extraction procedure being compared to a hierarchic logic plan circuit defined by a logic plan, the layout circuit and the logic plan circuit having sub-circuits, comprising the steps of:

• in a step 1, canceling terminals of a sub-circuit that are not connected to any component of this sub-circuit within this sub-circuit or are not connected to any occurrence of a lower-ranking sub-circuit that belongs to at least one next-lower hierarchy level;
• in a step 2, combining terminals of a sub-circuit that are externally connected to one another in all occurrences of a respective sub-circuit to form a common terminal, whereby this ensues across all hierarchy levels;
• in a step 3, canceling terminals of a sub-circuit that do not have an external connection to at least one component of another sub-circuit of the sub-circuits in any occurrence of this sub-circuit as external terminal on the respective hierarchy level;
• in a step 4, performing steps 1, 2 and 3 for each hierarchial level of each of the layout circuit and the hierarchic logic plan circuit such that a number of terminals of sub-circuits of each hierarchy level is minimal;
• in a step 5, forming pairs of potentially equivalent sub-circuits in that corresponding sub-circuits with a common name are sought in the layout circuit and in the logic plan circuit and are only allocated to one another for sub-circuits having an identical number of terminals;
• in a step 6, replacing occurrences of sub-circuits, to which a partner in the respectively other circuit is allocated, by a macro component that cannot be further detailed, insofar as at least all terminals of both occurrences of sub-circuits are completely allocated to one another;
• in a step 7, partially expanding occurrences of sub-circuits, to which no partner in the respectively other circuit is allocated, by switching to a lower hierarchy level until at least one occurrence of a sub-circuit is again present for which a partner in the respectively other circuit exists with allocated terminals, and replacing the respective occurrence of the respective lower-ranking sub-circuit by a respective macro component;
• in a step 8, further partially expanding occurrences of sub-circuits to which a partner in the respectively other circuit is allocated and wherein all terminals of both occurrences cannot be allocated to one another, or suppressing comparison of the higher-ranking circuit parts;
• in a step 9, further partially expanding occurrences of sub-circuits that do not occur an identical number of times in both circuits until a plurality of occurrences of all sub-circuits respectively corresponding to one another coincides, thereby reshaping internal hierarchies of a pair of potentially equivalent sub-circuits into isomorphic hierarchies;
• and
• in a step 10, performing steps 6, 7, 8 and 9 with regards to each of lower-ranking sub-circuits occurring in the respective sub-circuits to be compared.