US 5,671,393 A · Shared memory system and arbitration method and system

Abstract

A shared memory system and an arbitrating method and system. When the processing is distributed over a plurality of CPUs (e.g., CPUA and CPUB) and if it is desired that a shared memory is used to transfer data between the CPUs, a clock CKG indicating the CPUA access timing clock is generated. A gate signal G indicating the access right to the shared memory is generated in synchronism with the clock CKG. When either of the CPUs requests the access to the shared memory, it makes the corresponding chip select signal CSA.sup.- or CSB.sup.- L-level. The access right is always directed to the CPUA and switched to the CPUB in response to the access demand from the CPUB. After one access has completed, the CPUB makes CSB.sup.- H-level. Thus, the access right is switched to the CPUA. After one access has terminated, the CPUA makes CSA.sup.- H-level. If the CPUB requests the access at this time, the access right is switched to the CPUB. If the CPUB does not request the access, the access right is maintained at the CPUA. The CPUA and CPUB are synchronized with each other through a wait signal WAITA.sup.-. When the shared memory is to be accessed, no software is required. The speed of data transfer can be increased and the loads on the CPUs will not influence each other.

Claims7

Dependent claims

A shared memory system comprising:

a shared memory accessible by a preferred processor, which is that processor of a plurality of processors that currently has an access right, the access right being a right to access to the shared memory in synchronization with a processor specific clock signal, the processor specific clock signal being generated in the preferred processor and being independent from other of the plurality of processors;
and
arbitrating means for arbitrating access requests among the plurality of processors to give an access right to one of said plurality of processors, said arbitrating means comprising:
means for causing the giving up of the access of a first processor of said plurality of processors in response to the rising or falling of the processor specific clock signal having a predetermined frequency;
means for giving the access right to a second processor of said plurality of processors when said second processor is holding an access request at a point of time when the access right has been given up;
and
means for returning the access right to said first processor when no other processors of said plurality of processors are holding access requests and said first processor is holding an access request at the point of time when the access right has been given up.

4 more elements

Dependencies are inferred from the claim text.

Shared memory system and arbitration method and system

Life of this patent

Shared memory system and arbitration method and system

Life of this patent

Abstract

Claims7