Work station with a DMA controller having extended addressing capability
AssigneeNCR Corporation
InventorAnton Goeppel
Life of this patent
Estimating the term…
Abstract
A DMA controller is connected to a CPU in a work station. The controller includes a multiple byte memory address register (MAR), and a pointer register connected between the CPU and MAR. The pointer register is responsive to a command from the CPU to give the CPU successive access to the byte positions of the MAR for writing a memory address thereto. The DMA controller may also include a single byte register associated with the pointer register and connected between the CPU and MAR. The CPU writes an address to the MAR one byte at a time via the single byte register. Preferably, the MAR has a capacity of four 8 bit bytes.
Claims8
A work station including a CPU connected to a DMA controller, said controller comprising:
- a multiple byte memory address register (MAR) for storing a multiple byte memory address;
- and
- a pointer register connected between the CPU and MAR;
- wherein said pointer register is responsive to a command from said CPU to give said CPU successive access to the byte positions of said MAR for writing a memory address thereto.
A work station including a CPU connected to a microchannel bus through a single integrated microchip interface block, wherein said block operates with a timing independent of that of said CPU, and wherein said block comprises:
- a DMA controller;
- an interface circuit enabling communication between said DMA controller and said CPU;
- a synchronizer;
- and
- an internal bus connecting said DMA controller, interface circuit and synchronizer;
- wherein said DMA controller includes:
- a multiple byte memory address register (MAR) for storing a multiple byte memory address;
- a pointer register connected between said CPU and MAR;
- and
- a single byte register associated with said pointer register and connected between said CPU and MAR;
- wherein said pointer register is responsive to a command from said CPU to give said CPU successive access to the byte positions of said MAR for writing a memory address thereto;
- and
- wherein said CPU writes an address to said MAR one byte at a time via said single byte register.
Dependencies are inferred from the claim text.