US 5,671,370 A · Alternating data valid control signals for high performance data transfer

Abstract

A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.

Claims17

Dependent claims

A method of transferring data between devices in a data processing system connected by a system bus, comprising the steps of:

providing at least first and second data valid signals on first and second data valid lines in said system bus;
placing first data from a first providing device on said system bus, and activating said first data valid signal on said first data valid line;
placing second data from a second providing device on said system bus, and activating said second data valid signal on said second data valid line;
and
reading said first or second data, by a receiving device, when either said first or second data valid signal is active.

2 more elements

Dependencies are inferred from the claim text.

Alternating data valid control signals for high performance data transfer

Life of this patent

Alternating data valid control signals for high performance data transfer

Life of this patent

Abstract

Claims17