Data processing system for performing efficient fuzzy logic operations and method therefor

A data processing system for performing efficient fuzzy logic operations comprising:

• an instruction decoder having an input for receiving an instruction, and an output for providing a plurality of control signals;
• and
• an execution unit having a control input coupled to the output of the instruction decoder, and a data terminal coupled to an information bus;
• the instruction decoder controlling the execution unit to cause the execution unit to receive an input value via the data terminal and to determine a degree of membership of the input value in a membership function, in response to a fuzzy membership instruction;
• the instruction decoder further controlling the execution unit to determine whether the membership function is a last membership function of a plurality of membership functions;
• wherein the execution unit comprises:
• a condition code register having a plurality of condition code bits including a carry bit, and having a control input terminal for receiving a termination signal, the condition code register setting the carry bit in response to an activation of the termination signal;
• and
• a flag generation logic circuit having a control input coupled to the instruction decoder, and an output terminal for providing the termination signal, the flag generation logic circuit activating the termination signal in response to the instruction decoder determining that the membership function is the last membership function of the plurality of membership functions.

A method, in a data processing system, for determining whether a membership function is a last membership function of a plurality of membership functions while determining a degree of membership in at least one of the plurality of membership functions of an observed variable input point, comprising the steps of:

• (a) receiving an instruction from an instruction set comprising a plurality of instructions for determining the degree of membership of the observed variable input point;
• (b) detecting first and second boundary values defining a boundary of each of the plurality of membership functions;
• (c) successively testing each of the first and second boundary values of each of the plurality of membership functions to determine whether the boundary comprises an endpoint of the plurality of membership functions;
• (d) indicating that a membership function being tested is the last membership function of the plurality of membership functions by providing a termination signal to signal a termination of the step of successively testing relative to the observed variable input point and
• (e) placing a selected bit in a condition code register in a predetermined logic state.