High speed digital image pattern matching circuit

A high speed digital image pattern matching circuit comprising:

• a signal separator for separating an analog image signal into an analog luminance signal, a horizontal synchronization signal and a vertical synchronization signal;
• a synchronizing control circuit for generating synchronizing control signals according to the horizontal synchronization signal and the vertical synchronization signal separated by the signal separator, a frame horizontal size signal and a frame vertical size signal;
• a first counter for counting the synchronizing control signal and for generating a location value for a pattern being used for matching;
• an A/D converter for converting the analog luminance signal separated by the signal separator into a digital image signal using a quantization constant;
• a first threshold latch section and a second threshold latch section for storing and generating thresholds for modelling the digital image signal;
• a first comparator for sequentially comparing the bits of the digital image signal and the thresholds stored in the first threshold latch and the second threshold latch during one cycle of the synchronizing control signal and for generating an image modelling signal comprising the compared results sequentially generated by the first comparator;
• a first blocking means and a second blocking means for blocking the image modeling signal to have the same size as a reference model;
• a first reference model latch section and a second reference model latch section for storing and generating reference models;
• a bit comparator for performing a logical exclusive-OR function between the output signals of the first and second blocking means and the reference models of the first and second reference model latches;
• a logical 1 counter for counting the number of logical 1 bits output from the bit comparator;
• a second comparator for comparing a matching threshold with the output signal of the logical 1 counter and for generating a writing control signal when the matching threshold is larger than the output signal;
• a second counter for counting the writing control signal of the second comparator;
• and
• a memory for storing the output signal of the first counter in an address designated by the second counter according to the writing control signal (WR).