US 5,671,260 AGranted

Digital processing apparatus using two synchronization signals

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsEiji Yamauchi, Kiyokazu Hashimoto, Hidemi Oka, Takao Kashiro, Iwao Hidaka, Yoshiki Yamamoto

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Abstract

The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

Claims13

Dependent claims

A digital processing apparatus for processing an analog source signal including a first synchronization signal having a first predetermined frequency and a second synchronization signal having a second predetermined frequency smaller than said first predetermined frequency comprising:

a first reference signal generation means for generating a first reference signal based on said first synchronization signal;
a second reference signal generation means for generating a second reference signal based on said second synchronization signal;
a first clock signal generation means for generating a first clock signal whose phase is locked on said first reference signal;
an analog to digital converter means for sampling said analog source signal with respect to said first clock signal to generate a digitized source signal;
a memory means for storing at least one field of said digitized source signal;
a write control means for controlling said memory means, to store said digitized source signal, based on said first reference signal and said first clock signal;
a third reference signal generation means for generating a third reference signal and a fourth reference signal based on a second clock signal, said third reference signal and said fourth reference signal each having a respective predetermined frequency, that is a submultiple of said second clock signal;
a second clock signal generation means for generating said second clock signal synchronized with said second reference signal and said third reference signal;
and
a read control means for controlling said memory means, for reading said stored digitized source signal from said memory means, based on said fourth reference signal and said second clock signal.

7 more elements

a first reference signal generation means for generating a first reference signal based on said first synchronization signal;
a second reference signal generation means for generating a second reference signal based on said second synchronization signal;
a first clock signal generation means for generating a first clock signal whose frequency is constant, said first clock signal having a phase;
a second clock signal generation means for shifting the phase of said first clock signal in response to said first reference signal to generate a second clock signal, said second clock signal having a phase which is locked on said first synchronization signal;
an analog to digital convertor means for sampling said analog source signal with respect to said second clock signal to generate a first digitized source signal;
a phase converter means for converting the phase of said second clock signal into the phase of said first clock signal and maintaining a relative timing between said first reference signal and said first digitized source signal for generating:
(a) a third reference signal,
(b) a fourth reference signal, and
(c) a second digitized source signal, based on:
(a) said first reference signal,
(b) said second reference signal, and
(c) said first digitized source signal, respectively;
a memory means for storing at least one field of said second digitized source signal;
a write control means for controlling said memory means, to store said second digitized source signal, based on:
(a) said first clock signal,
(b) said third reference signal, and
(c) said fourth reference signal;
a third clock signal generation means for generating a third clock signal synchronized with said second reference signal and a fifth reference signal;
and
a fifth reference signal generation means for generating said fifth reference signal and a sixth reference signal based on said third clock signal, said fifth reference signal and said sixth reference signal each having a respective predetermined frequency that is a submultiple of said third clock signal;
a read control means for controlling said memory means, for reading said stored second digitized source signal from said memory means, based on said sixth reference signal and said third clock signal.

18 more elements

first reference signal generation means for generating a first reference signal based on said first synchronization signal;
second reference signal generation means for generating a second reference signal based on said second synchronization signal;
first clock signal generation means for generating a first clock signal, said first clock signal having a constant frequency;
second clock signal generation means for generating a second clock signal, said second clock signal having a phase locked on said first synchronization signal by shifting a phase of said first clock signal responsive to said first reference signal;
third clock signal generation means for generating a third clock signal and a third synchronization signal each having a respective phase locked on said first synchronization signal;
synchronization judging means for determining if the respective phases of said first reference signal and said third synchronization signal are within a predetermined range;
switch means for selectively outputting:
(a) one of said first reference signal and said third synchronization signal as a third reference signal,
(b) one of said second clock signal and said third clock signal as a fourth clock signal, and
(c) one of said first clock signal and said third clock signal as a fifth clock signal said fifth clock signal having a phase.
analog to digital convertor means for generating a first digitized source signal by sampling said analog source signal based on said fourth clock signal;
phase converter means for convening the respective phases of:
(a) said second reference signal,
(b) said third reference signal, and
(c) said first digitized source signal
into the phase of said fifth clock signal keeping a relative timing between said third reference signal and said first digitized source signal to generate a fourth reference signal, a fifth reference signal, and a second digitized source signal respectively;
memory means for storing at least one field of said second digitized source signal;
write control means for controlling said memory means, for storing said second digitized source signal, based on:
(a) said fourth reference signal,
(b) said fifth reference signal, and
(c) said fifth clock signal;
fourth clock signal generation means for generating a sixth clock signal synchronized with said second reference signal and a seventh reference signal;
third reference signal generation means for generating said seventh reference signal and an eighth reference signal based on:
(a) said sixth clock signal,
(b) said seventh reference signal, and
(c) said eighth reference signal,
each having a predetermined frequency that is a submultiple of said sixth clock signal;
and
read control means for controlling said memory means, for reading said stored second digitized source signal from said memory means, based on said eighth reference signal and said sixth clock signal.

26 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/534,512Filed 27 Sep 1995
Priority: JP 6-23289028 Sep 1994
Granted: 23 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H04N 5/956
Time-base error compensation: by using a digital memory with independent write-in and read-out clock generators
H04N 5/926
Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback: by pulse code…
H04N 5/937
Regeneration of the television signal or of selected parts thereof: by assembling picture element blocks in an intermediate store
H04N
Pictorial communication