Clock recovery circuit

Abstract

A clock recovery circuit includes a resonant circuit which has a varactor diode and is driven into oscillation at a variable frequency in response to a control voltage fed to the varactor diode. Basically, the resonant circuit is tuned into the clock frequency of an incoming binary data signal. The clock recovery circuit provides a clock signal which is associated with a data output signal. The desired transition timing of the clock signal is at mid-point of the incoming binary data signal. When the transition timing is advanced or delayed from the mid-point due to changes in the resonant frequency of the circuit, the control voltage changes, with the result that the tuning frequency of the resonant circuit is varied. In response to the change of the resonant frequency, the transition timing of the clock output signal is delayed or advanced. This condition is detected and the control voltage fed to the varactor is changed, resulting in achievement of correct transition timing. Use of digital rather than analog integration in the control loop ensures that the adjustment will not be lost during periods in which no incoming signal is present.

Dependencies are inferred from the claim text.