Clock recovery circuit and receiver using same

A clock recovery circuit for a data stream, comprising:

• an edge detection circuit which receives the data stream and generates edge detection signals indicating high-to-low and low-to-high transitions in the data stream;
• reference clock generation circuitry which generates a plurality of reference clock signals shifted in phase with respect to one another;
• phase quantizing circuitry, responsive to the edge detection signals and the plurality of reference clock signals, which generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals;
• and
• clock selection circuitry, having inputs coupled to the plurality of reference clock signals, and responsive to the quantization signal to select the indicated reference clock signal;
• and
• wherein the reference clock generation circuitry includes:
• a local clock input to receive a local clock;
• a reference generator responsive to the local clock to generate a first reference wave and a second reference wave out of phase relative to the first reference wave;
• and
• a plurality of reference clock generators which generate respective reference clock signals in response to the first reference wave and second reference wave, each of the reference clock generators generating a reference clock signal having a phase determined by relative amplitudes of the first and second reference waves.

An apparatus for receiving transmitted, non-phase encoded serial data from a wireless communication medium, comprising:

• a receiver adapted to produce a local, non-phase encoded serial data stream from the transmitted serial data in the wireless communication medium;
• a local clock;
• edge detection circuitry which receives the local, non-phase encoded data stream and generates edge detection signals indicating transitions in the local data stream;
• reference clock generation circuitry which, in response to the local clock, generates a plurality of reference clock signals shifted in phase with respect to one another;
• phase quantizing circuitry, responsive to the edge detection signals and the plurality of reference clock signals, which generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals;
• clock selection circuitry, having inputs coupled to the plurality of reference clock signals and an output, and responsive to the quantization signal to supply the indicated reference clock signal as a recovered clock signal on its output;
• and
• data recovery circuitry, connected to the receiver and the output of the clock selection circuitry, to produce a recovered data signal in response to the local, non-phase encoded data stream and the recovered clock signal;
• and
• wherein the reference clock generation circuitry includes:
• a reference generator responsive to the local clock to generate a first reference wave and a second reference wave out of phase relative to the first reference wave;
• and
• a plurality of reference clock generators which generate respective reference clock signals in response to the first reference wave and second reference wave, each of the reference clock generators generating a reference clock signal having a phase determined by relative amplitudes of the first and second reference waves.

An apparatus for receiving transmitted, non-phase encoded serial data from a wireless communication medium, comprising:

• a receiver adapted to produce a local, non-phase encoded serial data stream from the transmitted serial data in the wireless communication medium;
• a local clock;
• edge detection circuitry which receives the local, non-phase encoded data stream and generates edge detection signals indicating transitions in the local data stream;
• a reference generator responsive to the local clock to generate a first reference wave and a second reference wave out of phase relative to the first reference wave;
• a plurality of reference clock generators which generate a plurality of reference clock signals in response to the first reference wave and second reference wave, each of the reference clock generators generating a respective reference clock signal in the plurality of reference clock signals having a phase determined by relative amplitudes of the first and second reference waves;
• phase quantizing circuitry, responsive to the edge detection signals and the plurality of reference clock signals, which generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals, including a plurality of memory elements, having respective inputs coupled to corresponding ones of the plurality of reference clock signals, which in response to the edge detection signal store a state of the plurality of reference clock signals, a digital decoder responsive to the stored state to produce a state decode signal, and a recursive digital filter which filters the state decode signal to produce the quantization signal;
• clock selection circuitry, having inputs coupled to the plurality of reference clock signals and an output, and responsive to the quantization signal to supply the indicated reference clock signal as a recovered clock signal on its output;
• and
• data recovery circuitry, connected to the receiver and the output of the dock selection circuitry, to produce a recovered data signal in response to the local, non-phase encoded data stream and the recovered clock signal.

A clock recovery circuit for a data stream, comprising:

• an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream;
• reference clock generation circuitry which generates a plurality of reference clock signals shifted in phase with respect to one another;
• phase quantizing circuitry, responsive to the edge detection signals and the plurality of reference clock signals, which generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals;
• and
• clock selection circuitry, having inputs coupled to the plurality of reference clock signals, and responsive to the quantization signal to select the indicated reference clock signal;
• and
• wherein the reference clock generation circuitry includes:
• a local clock input to receive a local clock;
• a reference generator responsive to the local clock to generate a first reference wave and a second reference wave one quarter cycle out of phase relative to the first reference wave;
• a monolithic resistor ladder receiving the first and second reference waves;
• and
• a plurality of reference clock generators, coupled to the resistor ladder, which generate respective reference clock signals in response to relative magnitudes of the first reference wave and second reference wave set by the resistor ladder.