Semiconductor memory of xN type having error correcting circuit by parity
AssigneeFujitsu Limited
InventorsMasaaki Higashitani, Masatomo Hasegawa
Life of this patent
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Abstract
A memory device for storing data of a multi-bit structure in a plurality of memory cell blocks has a parity cell block having the same structure as the memory cell block. If read data contains an error bit, this error bit is corrected by an EOR calculation of correct bits and a parity bit. The address of an error bit is written in a defective cell memory made of fuses for example. In the case of a flash memory, a parity calculation and a parity data write operation are performed at the same time when data is written.
Claims12
A semiconductor memory device having a memory cell array divided into a plurality of cell blocks, comprising:
- n memory cell blocks, for storing n-bit data, one bit of the n-bit data being stored per one memory cell block at a same address thereof;
- a parity memory unit for storing a parity of said n-bit data at an address corresponding to the address where said n-bit data is stored;
- a defective output memory unit for storing defective block data indicating a defective memory cell block among said n memory cell blocks;
- and
- a data correction circuit for correcting data in said defective memory cell block by calculating an exclusive OR of (n-1) bits of said n-bit data and the parity, the (n-1) bits being stored in said memory cell blocks at the same address except for one memory cell block indicated by said defective output memory unit, the parity being stored in said parity memory unit at the corresponding same address.
A semiconductor memory device comprising:
- a memory cell army of a multi-bit structure having n memory cell blocks of a mask ROM structure, for storing n-bit data, one bit of the n-bit data being stored per one memory cell block at a same address per memory cell block as other bits of the n-bit data being stored;
- a parity cell block for storing parity data for said n-bit data at an address corresponding to the address where said n-bit data is stored, said parity data being an EOR value of said n-bit data;
- a defective output memory unit for storing defective block data indicating a defective one of said memory cell blocks;
- and
- a data correction circuit for correcting an error bit among said n-bit data, by calculating an exclusive OR of (n-1) bits of said n-bit data and the parity, the (n-1) bits being stored in said memory cell blocks at the same address except for one memory cell block indicated by said defective output memory unit, the parity being stored in said parity cell block at the corresponding same address, and to correct data among said n-bit data read from said memory cell blocks.
Dependencies are inferred from the claim text.