US 5,671,238 AGranted

Method and circuitry for generating r-bit parallel CRC code for an l-bit data source

AssigneeNational Science Council of R.O.C.

InventorsKim-Joan Chen, Ching-Long Chang

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method for generating r-bit parallel CRC code for a data source grouped into at least one successive p-bit parallel data group and a q-bit parallel data group is disclosed. The number q is less than the number p. The method includes the steps of: providing a data processing unit which has an output side and an input side that is adapted to receive successively the p-bit and q-bit parallel data groups, the processing unit reflecting one of the p-bit parallel data groups at the input side to the output side when the p-bit parallel data group is present at the input side, the processing unit adding a bit string to the q-bit parallel data group such that sum of the number q and number of bits in the bit string is equal to the number p, the processing unit presenting the q-bit parallel data group and the bit string at the output side when the q-bit parallel data group is present at the input side; providing a binary output generating unit which operates in response to data at the output side to produce an r-bit parallel initial CRC code according to a predefined generating polynomial function; and providing a code correcting unit which receives the r-bit parallel initial CRC code from the generating unit and which operates in response to the parallel initial CRC code to produce an r-bit parallel final CRC code according to a predefined code correcting function.

Claims11

Dependent claims

A method for generating r-bit parallel CRC code for an L-bit data source, the L-bit data source being grouped into successive at least one p-bit parallel data group and a q-bit parallel data group, the number q being less than the number p, said method comprising the steps of:

providing a data processing unit which has an output side and an input side that is adapted to be connected electrically to said data source and that is adapted to receive successively said p-bit parallel data group and said q-bit parallel data group, said data processing unit reflecting one of said p-bit parallel data groups at said input side to said output side when said one of said p-bit parallel data groups is present at said input side, said data processing unit adding a bit string to said q-bit parallel data group such that sum of the number q and number of bits in said bit string is equal to the number p, said data processing unit presenting said q-bit parallel data group and said bit string at said output side when said q-bit parallel data group is present at said input side;
providing a binary output generating unit which is connected electrically to said output side of said data processing unit and which operates in response to data at said output side of said data processing unit to produce an r-bit parallel initial CRC code according to a predefined generating polynomial function;
and
providing a code correcting unit which is connected electrically to said binary output generating unit and which receives said r-bit parallel initial CRC code therefrom, said code correcting unit operating in response to said r-bit parallel initial CRC code to produce an r-bit parallel final CRC code according to a predefined code correcting function.

1 more element

A universal parallel CRC generating circuitry for generating an r-bit parallel CRC code for an L-bit data source, the L-bit data source being grouped into successive at least one p-bit parallel data group and a q-bit parallel data group, the number q being less than the number p, said parallel CRC generating circuitry comprising:

a data processing unit having an output side and an input side which is adapted to be connected electrically to said data source and which is adapted to receive successively said p-bit parallel data group and said q-bit parallel data group, said data processing unit reflecting one of said p-bit parallel data groups at said input side to said output side when said one of said p-bit parallel data groups is present at said input side, said data processing unit adding a bit string to said q-bit parallel data group such that sum of the number q and number of bits in said bit string is equal to the number p, said data processing unit presenting said q-bit parallel data group and said bit string at said output side when said q-bit parallel data group is present at said input side;
a binary output generating unit connected electrically to said output side of said data processing unit and operating in response to data at said output side of said data processing unit to produce an r-bit parallel initial CRC code according to a predefined generating polynomial function;
and
a code correcting unit connected electrically to said binary output generating unit and receiving said r-bit parallel initial CRC code therefrom, said code correcting unit operating in response to said r-bit parallel initial CRC code to produce an r-bit parallel final CRC code according to a predefined code correcting function.

1 more element

Dependencies are inferred from the claim text.